chips/marina/electric/latchesK.delib/aLatchGallery.sch

   1 HlatchesK|8.10k
   2
   3 # Cell aLatchGallery;1{sch}
   4 CaLatchGallery;1{sch}||schematic|1206032594290|1221430775610|
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 Ilatch1in10A;1{ic}|latch1in@0||-24|0|||D5G4;
   7 Ilatch1in30A;1{ic}|latch1in@1||0|12|||D5G4;
   8 Ilatch1in40B;1{ic}|latch1in@2||24|12|||D5G4;
   9 Ilatch1in60C;1{ic}|latch1in@3||36|12|||D5G4;
  10 Ilatch1in10B;1{ic}|latch1in@4||-12|12|||D5G4;
  11 Ilatch1in09.6Bi;1{ic}|latch1in@5||-36|12|||D5G4;
  12 Ilatch1in09.6B;1{ic}|latch1in@6||-24|12|||D5G4;
  13 Ilatch1in20B;1{ic}|latch1in@7||12|12|||D5G4;
  14 Ilatch2in10A;1{ic}|latch2in@0||-24|-12|||D5G4;
  15 Ilatch2in10Aimc;1{ic}|latch2in@1||-12|0|||D5G4;
  16 Ilatch2in10Alo;1{ic}|latch2in@2||0|0|||D5G4;
  17 Ilatch2in10Alomc;1{ic}|latch2in@3||12|0|||D5G4;
  18 Ilatch2in20A;1{ic}|latch2in@4||-12|-12|||D5G4;
  19 Ilatch2in60C;1{ic}|latch2in@5||0|-12|||D5G4;
  20 Ilatch2in60Cmux;1{ic}|latch2in@6||12|-12|||D5G4;
  21 Imlat1in10;1{ic}|mlat1in1@1||-12|-24|||D5G4;
  22 Imlat1in10i;1{ic}|mlat1in1@2||0|-24|||D5G4;
  23 Imlat1in5i;1{ic}|mlat1in5@0||-32|-24|||D5G4;
  24 Imlat2in10;1{ic}|mlat2in1@1||12|-24|||D5G4;
  25 Imlat2in10i;1{ic}|mlat2in1@2||24|-24|||D5G4;
  26 Imlat2in20;2{ic}|mlat2in2@0||34|-24|||D5G4;
  27 Imlat2in5i;1{ic}|mlat2in5@0||-23|-24|||D5G4;
  28 Ngeneric:Invisible-Pin|pin@3||0|48|||||ART_message(D5G6;)SaLatchGallery
  29 Ngeneric:Invisible-Pin|pin@4||0|42|||||ART_message(D5G3;)Sies 13 September 2008
  30 Ngeneric:Invisible-Pin|pin@5||-26|39|||||ART_message(D3G4;)S[A latches have one amplifier,B latches have two amplifiers,C latches have three amplifiers,Latches without wings use,LO threshold amplifiers]
  31 Ngeneric:Invisible-Pin|pin@6||-45|-24|||||ART_message(D5G3;)SmuxLatches
  32 X