chips/marina/electric/latchesK.delib/latch1in09.6Bi.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 # Cell latch1in09.6Bi;1{lay}
   8 Clatch1in09.6Bi;1{lay}||cmos90|1205073999618|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982205540
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 IlatchPartsK:latchAmp09.6B;1{lay}|latchAmp@2||17.5|0|||D5G4;
  11 NMetal-1-Pin|pin@20||0.3|-25||||
  12 Iraw1inLatchF;1{lay}|raw1inLa@1||-7.5|0|||D5G4;
  13 Ametal-2|net@39||6.2|S1800|raw1inLa@1|gnd_1|-7.7|0|latchAmp@2|gnd|5|0
  14 Ametal-2|net@40||6.2|S0|latchAmp@2|vdd|5|-50|raw1inLa@1|vdd_4|-7.7|-50
  15 Ametal-2|net@41||6.2|S0|latchAmp@2|vdd_2|5|50|raw1inLa@1|vdd_3|-7.7|50
  16 Ametal-1|net@42|||S900|raw1inLa@1|out[F]|0.3|-12.5|pin@20||0.3|-25
  17 Ametal-1|net@43|||S1800|pin@20||0.3|-25|latchAmp@2|in|11.5|-25
  18 Egnd||D5G2;|raw1inLa@1|gnd|G
  19 Egnd_1||D5G2;|latchAmp@2|gnd_1|G
  20 Ehcl||D5G2;|raw1inLa@1|hcl|I
  21 Ein[1]||D5G2;|raw1inLa@1|in[1]|I
  22 Eout[1]||D5G2;|latchAmp@2|out[1]|O
  23 Evdd||D5G2;|raw1inLa@1|vdd|P
  24 Evdd_1||D5G2;|latchAmp@2|vdd_1|P
  25 Evdd_2||D5G2;|raw1inLa@1|vdd_2|P
  26 Evdd_3||D5G2;|latchAmp@2|vdd_3|P
  27 X