chips/marina/electric/latchesK.delib/latch1in10Aw.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 LwiresL|wiresL
   8
   9 # Cell latch1in10Aw;1{lay}
  10 Clatch1in10Aw;1{lay}|latch1in10A|cmos90|1194236252807|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 Iraw1inLatchF;1{lay}|hi1inLat@0||0|0|||D5G4;
  13 IlatchPartsK:latchAmp10;1{lay}|latchAmp@0||39|0|||D5G4;
  14 NMetal-1-Pin|pin@3||7.8|-25||||
  15 NMetal-2-Pin|pin@4||47|50||||
  16 IlatchPartsK:shoulderFillWide;1{lay}|shoulder@0||40|50|X||D5G4;
  17 IwiresL:wellContacts13;1{lay}|wellCont@1||19.5|0|||D5G4;
  18 Ametal-1|net@9|||S0|latchAmp@0|in|35.5|-25|pin@3||7.8|-25
  19 Ametal-2|net@14||6.2|S0|wellCont@1|vdd_1|15|50|hi1inLat@0|vdd_3|-0.2|50
  20 Ametal-2|net@15||6.2|S1800|hi1inLat@0|gnd_1|-0.2|0|wellCont@1|gnd|15|0
  21 Ametal-2|net@16||6.2|S1800|hi1inLat@0|vdd_4|-0.2|-50|wellCont@1|vdd|15|-50
  22 Ametal-2|net@17||6.2|S1800|wellCont@1|gnd_1|24|0|latchAmp@0|gnd|31|0
  23 Ametal-2|net@18||6.2|S0|latchAmp@0|vdd|31|-50|wellCont@1|vdd_2|24|-50
  24 Ametal-2|net@19||6.2|S0|pin@4||47|50|wellCont@1|vdd_3|24|50
  25 Ametal-1|net@20|||S2700|pin@3||7.8|-25|hi1inLat@0|out[F]|7.8|-12.5
  26 Egnd||D5G2;|hi1inLat@0|gnd|G
  27 Egnd_1||D5G2;|latchAmp@0|gnd_1|G
  28 Ehcl||D5G2;|hi1inLat@0|hcl|I
  29 Ehcl_1||D5G2;|hi1inLat@0|hcl_1|I
  30 Ein[1]||D5G2;|hi1inLat@0|in[1]|I
  31 Eout[1]||D5G2;|latchAmp@0|out[1]|O
  32 Evdd||D5G2;|hi1inLat@0|vdd|P
  33 Evdd_1||D5G2;|latchAmp@0|vdd_1|P
  34 Evdd_2||D5G2;|hi1inLat@0|vdd_2|P
  35 Evdd_3||D5G2;|pin@4||P
  36 X