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[fleet.git] / chips / marina / electric / latchesK.delib / latch1in30Am1w.lay
1 HlatchesK|8.10k
2
3 # External Libraries:
4
5 LlatchPartsK|latchPartsK
6
7 LwiresL|wiresL
8
9 # Cell latch1in30Am1w;1{lay}
10 Clatch1in30Am1w;1{lay}|latch1in30A|cmos90|1197076555516|1238257435226||ATTR_NCC(D5G3;NTX30;Y70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/",exportsConnectedByParent hcl hcl_1]
11 Ngeneric:Facet-Center|art@0||0|0||||AV
12 NX-Metal-1-Metal-2-Con|contact@4||11.6|28||||
13 NX-Metal-1-Metal-2-Con|contact@5||11.6|-28||||
14 NX-Metal-1-Metal-2-Con|contact@6||37.2|-28||||
15 NX-Metal-1-Metal-2-Con|contact@8||37.2|28||||
16 NMetal-1-Polysilicon-Con|contact@10||54|62||5.2||
17 IlatchPartsK:latchAmp30;1{lay}|latchAmp@2||7.6|0|X||D5G4;
18 NMetal-1-Pin|pin@21||54|63||||
19 Iraw1inLatchF;1{lay}|raw1inLa@1||45|0|X||D5G4;
20 IwiresL:wellContacts13;1{lay}|wellCont@1||28.4|0|||D5G4;
21 Ametal-2|net@39||6.2|S0|wellCont@1|gnd|23.9|0|latchAmp@2|gnd|22.6|0
22 Ametal-2|net@40||6.2|S1800|latchAmp@2|vdd|22.6|-50|wellCont@1|vdd|23.9|-50
23 Ametal-2|net@41||6.2|S1800|latchAmp@2|vdd_2|22.6|50|wellCont@1|vdd_1|23.9|50
24 Ametal-2|net@42||6.2|S1800|wellCont@1|vdd_3|32.9|50|raw1inLa@1|vdd_3|45.2|50
25 Ametal-2|net@43||6.2|S0|raw1inLa@1|gnd_1|45.2|0|wellCont@1|gnd_1|32.9|0
26 Ametal-2|net@44||6.2|S0|raw1inLa@1|vdd_4|45.2|-50|wellCont@1|vdd_2|32.9|-50
27 Ametal-1|net@66|||S2700|latchAmp@2|in_1|11.6|23.5|contact@4||11.6|28
28 Ametal-1|net@68|||S900|latchAmp@2|in|11.6|-25|contact@5||11.6|-28
29 Ametal-2|net@69|||S1800|contact@5||11.6|-28|contact@6||37.2|-28
30 Ametal-1|net@70|||S900|raw1inLa@1|out[F]|37.2|-12.5|contact@6||37.2|-28
31 Ametal-2|net@71|||S1800|contact@4||11.6|28|contact@8||37.2|28
32 Ametal-1|net@74|||S2700|raw1inLa@1|out[F]|37.2|-12.5|contact@8||37.2|28
33 APolysilicon|net@76|||S900|contact@10||54|59.4|raw1inLa@1|hcl|54|58.5
34 Ametal-1|net@80|||S1800|pin@21||54|63|contact@10||54|63
35 Egnd||D5G2;|raw1inLa@1|gnd|G
36 Egnd_2||D5G2;|latchAmp@2|gnd_1|G
37 Ehcl||D5G2;|pin@21||I
38 Ehcl_1||D5G2;|raw1inLa@1|hcl_1|I
39 Ein[1]||D5G2;|raw1inLa@1|in[1]|I
40 Eout[1]||D5G2;|latchAmp@2|out[1]|O
41 Evdd||D5G2;|raw1inLa@1|vdd_2|P
42 Evdd_1||D5G2;|latchAmp@2|vdd_1|P
43 Evdd_3||D5G2;|raw1inLa@1|vdd|P
44 Evdd_5||D5G2;|latchAmp@2|vdd_3|O
45 X