chips/marina/electric/latchesK.delib/latch1in40B.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 # Cell latch1in40B;1{lay}
   8 Clatch1in40B;1{lay}||cmos90|1205073999618|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 IlatchPartsK:latchAmp40Am1;1{lay}|latchAmp@0||18|0|||D5G4;
  11 NMetal-1-Pin|pin@8||-7.2|-25||||
  12 NMetal-1-Pin|pin@9||-7.2|24||||
  13 Iraw1inLatchT;1{lay}|raw1inLa@1||-15|0|||D5G4;
  14 Ametal-2|net@12||6.2|S1800|raw1inLa@1|vdd_3|-15.2|50|latchAmp@0|vdd|-6|50
  15 Ametal-2|net@13||6.2|S1800|raw1inLa@1|gnd_1|-15.2|0|latchAmp@0|gnd|-6|0
  16 Ametal-2|net@14||6.2|S1800|raw1inLa@1|vdd_4|-15.2|-50|latchAmp@0|vdd_1|-6|-50
  17 Ametal-1|net@17|||S900|raw1inLa@1|out[T]|-7.2|-12.5|pin@8||-7.2|-25
  18 Ametal-1|net@18|||S1800|pin@8||-7.2|-25|latchAmp@0|in|-2|-25
  19 Ametal-1|net@23|||S2700|raw1inLa@1|out[T]|-7.2|-12.5|pin@9||-7.2|24
  20 Ametal-1|net@24|||S1800|pin@9||-7.2|24|latchAmp@0|in_1|-2|24
  21 Egnd||D5G2;|raw1inLa@1|gnd|G
  22 Egnd_1||D5G2;|latchAmp@0|gnd_1|G
  23 Ehcl[A]|hcl|D5G2;|raw1inLa@1|hcl[A]|I
  24 EinA[1]|in[1]|D5G2;|raw1inLa@1|inA[1]|I
  25 Eout[1]||D5G2;|latchAmp@0|out[1]|O
  26 Evdd||D5G2;|raw1inLa@1|vdd|P
  27 Evdd_2||D5G2;|raw1inLa@1|vdd_2|P
  28 Evdd_3||D5G2;|latchAmp@0|vdd_2|P
  29 Evdd_4||D5G2;|latchAmp@0|vdd_3|P
  30 X