chips/marina/electric/latchesK.delib/latch1in60Cm1.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 LwiresL|wiresL
   8
   9 # Cell latch1in60Cm1;1{lay}
  10 Clatch1in60Cm1;1{lay}|latch1in60C|cmos90|1194627475361|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|FACET_characteristic_spacing()D[144.0,144.0]
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 Ngeneric:Essential-Bounds|art@1||-72|-72|||RR|A
  13 Ngeneric:Essential-Bounds|art@2||72|72||||A
  14 NX-Metal-1-Metal-2-Con|contact@1||-37.2|-28||||
  15 NX-Metal-1-Metal-2-Con|contact@2||-6|-28||||
  16 Iraw1inLatchF;1{lay}|hi1inLat@0||-45|0|||D5G4;
  17 IlatchPartsK:latchAmp60Cm1;1{lay}|latchAmp@0||40|0|||D5G4;
  18 IwiresL:select22;1{lay}|select22@0||-23|0|||D5G4;
  19 Ametal-2|net@18|||S1800|contact@1||-37.2|-28|contact@2||-6|-28
  20 Ametal-1|net@23|||S900|latchAmp@0|in|-6|-24|contact@2||-6|-28
  21 Ametal-2|net@33||6.2|S0|latchAmp@0|gnd|-13.5|0|hi1inLat@0|gnd_1|-45.2|0
  22 Ametal-2|net@35||6.2|S0|latchAmp@0|vdd_1|-13.5|50|hi1inLat@0|vdd_3|-45.2|50
  23 Ametal-2|net@36||6.2|S0|latchAmp@0|vdd|-13.5|-50|hi1inLat@0|vdd_4|-45.2|-50
  24 Ametal-1|net@45|||S2700|contact@1||-37.2|-28|hi1inLat@0|out[F]|-37.2|-12.5
  25 Egnd||D5G2;|hi1inLat@0|gnd|G
  26 Egnd_1||D5G2;|latchAmp@0|gnd_1|G
  27 Ehcl||D5G2;|hi1inLat@0|hcl|I
  28 Ehcl_1||D5G2;|hi1inLat@0|hcl_1|I
  29 Ein[1]|inS[1]|D5G2;|hi1inLat@0|in[1]|I
  30 Eout[1]|outS[1]|D5G2;|latchAmp@0|out[1]|O
  31 Evdd||D5G2;|hi1inLat@0|vdd|P
  32 Evdd_2||D5G2;|hi1inLat@0|vdd_2|P
  33 Evdd_3||D5G2;|latchAmp@0|vdd_2|P
  34 Evdd_4||D5G2;|latchAmp@0|vdd_3|P
  35 X