chips/marina/electric/latchesK.delib/latch1in60Cm2up.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 LwiresL|wiresL
   8
   9 # Cell latch1in60Cm2up;1{lay}
  10 Clatch1in60Cm2up;1{lay}|latch1in60C|cmos90|1194627475361|1241212843263||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982414663|FACET_characteristic_spacing()D[144.0,144.0]
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 Ngeneric:Essential-Bounds|art@1||-72|-72|||RR|A
  13 Ngeneric:Essential-Bounds|art@2||72|72||||A
  14 NX-Metal-1-Metal-2-Con|contact@3||64|10||||
  15 NX-Metal-1-Metal-2-Con|contact@4||-58.5|-10||||
  16 NX-Metal-1-Metal-2-Con|contact@5||-37.2|-28||||
  17 NX-Metal-1-Metal-2-Con|contact@6||-6|-28||||
  18 Iraw1inLatchF;1{lay}|hi1inLat@0||-45|0|||D5G4;
  19 IlatchPartsK:latchAmp60Cm1;1{lay}|latchAmp@0||40|0|||D5G4;
  20 NMetal-2-Pin|pin@0||55|10||||
  21 NMetal-2-Pin|pin@1||-52.5|-10||||
  22 IwiresL:select22;1{lay}|select22@0||-22.5|0|||D5G4;
  23 Ametal-2|net@33||6.2|S0|latchAmp@0|gnd|-13.5|0|hi1inLat@0|gnd_1|-45.2|0
  24 Ametal-2|net@35||6.2|S0|latchAmp@0|vdd_1|-13.5|50|hi1inLat@0|vdd_3|-45.2|50
  25 Ametal-2|net@36||6.2|S0|latchAmp@0|vdd|-13.5|-50|hi1inLat@0|vdd_4|-45.2|-50
  26 Ametal-2|net@46|||S1800|pin@0||55|10|contact@3||64|10
  27 Ametal-1|net@47|||S900|latchAmp@0|out[1]|64|13|contact@3||64|10
  28 Ametal-2|net@48|||S0|pin@1||-52.5|-10|contact@4||-58.5|-10
  29 Ametal-1|net@49|||S900|hi1inLat@0|in[1]|-58.5|-7|contact@4||-58.5|-10
  30 Ametal-1|net@54|||S900|hi1inLat@0|out[F]|-37.2|-12.5|contact@5||-37.2|-28
  31 Ametal-2|net@55|||S1800|contact@5||-37.2|-28|contact@6||-6|-28
  32 Ametal-1|net@56|||S900|latchAmp@0|in|-6|-24|contact@6||-6|-28
  33 Egnd||D5G2;|hi1inLat@0|gnd|G
  34 Egnd_1||D5G2;|latchAmp@0|gnd_1|G
  35 Ehcl||D5G2;|hi1inLat@0|hcl|I
  36 EinS[1]@907770434|inS[1]|D5G2;|pin@1||I
  37 EoutS[2]|outS[1]|D5G2;|pin@0||O
  38 Evdd||D5G2;|hi1inLat@0|vdd|P
  39 Evdd_2||D5G2;|hi1inLat@0|vdd_2|P
  40 Evdd_3||D5G2;|latchAmp@0|vdd_2|P
  41 Evdd_4||D5G2;|latchAmp@0|vdd_3|P
  42 X