chips/marina/electric/latchesK.delib/latch2in10Aimc.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 # Cell latch2in10Aimc;1{lay}
   8 Clatch2in10Aimc;1{lay}||cmos90|1194186085518|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 IlatchPartsK:latchAmp10;1{lay}|latchAmp@0||27|0|||D5G4;
  11 NMetal-2-Pin|pin@12||35|50||||
  12 NMetal-1-Pin|pin@23||10|-25||||
  13 Iraw2inLatchTmc;1{lay}|raw2inLa@0||2|0|X||D5G4;
  14 IlatchPartsK:shoulderFill;1{lay}|shoulder@0||35|50|X||D5G4;
  15 Ametal-2|net@52|||S0|latchAmp@0|gnd|19|0|raw2inLa@0|gnd|19|0
  16 Ametal-2|net@53|||S0|latchAmp@0|vdd|19|-50|raw2inLa@0|vdd|19|-50
  17 Ametal-1|net@54|||S0|latchAmp@0|in|23.5|-25|pin@23||10|-25
  18 Ametal-1|net@55|||S2700|pin@23||10|-25|raw2inLa@0|out[T]|10|-12.5
  19 Ametal-2|net@56||6.2|S0|pin@12||35|50|raw2inLa@0|vdd_1|27|50
  20 Egnd||D5G2;|raw2inLa@0|gnd_1|G
  21 Egnd_1||D5G2;|latchAmp@0|gnd_1|G
  22 Ehcl||D5G2;|raw2inLa@0|hcl|I
  23 Ehcl_1||D5G2;|raw2inLa@0|hcl_1|I
  24 EinA[1]||D5G2;|raw2inLa@0|inA[1]|U
  25 Emc||D5G2;|raw2inLa@0|mc|I
  26 Eout[1]||D5G2;|latchAmp@0|out[1]|O
  27 Evdd||D5G2;|raw2inLa@0|vdd_3|P
  28 Evdd_1||D5G2;|latchAmp@0|vdd_1|P
  29 Evdd_2||D5G2;|raw2inLa@0|vdd_2|P
  30 Evdd_3||D5G2;|pin@12||P
  31 X