chips/marina/electric/latchesK.delib/latch2in10Alo.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 # Cell latch2in10Alo;1{lay}
   8 Clatch2in10Alo;1{lay}||cmos90|1194186085518|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981714344
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NX-Metal-1-Metal-2-Con|contact@0||0|-22||||
  11 NX-Metal-1-Metal-2-Con|contact@1||17.5|-22||||
  12 Iraw2inLatchF;1{lay}|hi2inLat@2||-8|0|||D5G4;
  13 IlatchPartsK:latchAmp10;1{lay}|latchAmp@0||27|0|||D5G4;
  14 NMetal-2-Pin|pin@12||35|50||||
  15 NMetal-1-Pin|pin@14||17.5|-25||||
  16 IlatchPartsK:shoulderFillWide;1{lay}|shoulder@0||28|50|X||D5G4;
  17 Ametal-2|net@3|||S0|contact@1||17.5|-22|contact@0||0|-22
  18 Ametal-2|net@31|||S0|latchAmp@0|gnd|19|0|hi2inLat@2|gnd_1|19|0
  19 Ametal-2|net@32|||S0|latchAmp@0|vdd|19|-50|hi2inLat@2|vdd_4|19|-50
  20 Ametal-2|net@33||6.2|S1800|hi2inLat@2|vdd_3|19|50|pin@12||35|50
  21 Ametal-1|net@34|||S2700|contact@0||0|-22|hi2inLat@2|out[F]|0|-12.5
  22 Ametal-1|net@36|||S0|latchAmp@0|in|23.5|-25|pin@14||17.5|-25
  23 Ametal-1|net@37|||S2700|pin@14||17.5|-25|contact@1||17.5|-22
  24 Egnd||D5G2;|hi2inLat@2|gnd|G
  25 Egnd_1||D5G2;|latchAmp@0|gnd_1|G
  26 Ehcl[A]||D5G2;|hi2inLat@2|hcl[A]|I
  27 Ehcl[B]||D5G2;|hi2inLat@2|hcl[B]|I
  28 Ehcl_1||D5G2;|hi2inLat@2|hcl_1|I
  29 EinA[1]||D5FLeave alone;G2;|hi2inLat@2|inA[1]|I
  30 EinB[1]||D5FLeave alone;G2;|hi2inLat@2|inB[1]|I
  31 Eout[1]||D5G2;|latchAmp@0|out[1]|O
  32 Evdd||D5G2;|hi2inLat@2|vdd|P
  33 Evdd_1||D5G2;|latchAmp@0|vdd_1|P
  34 Evdd_2||D5G2;|hi2inLat@2|vdd_2|P
  35 Evdd_3||D5G2;|pin@12||P
  36 X