chips/marina/electric/latchesK.delib/latch2in20A.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 # Cell latch2in20A;1{lay}
   8 Clatch2in20A;1{lay}||cmos90|1204627760999|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982287554
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NX-Metal-1-Metal-2-Con|contact@1||22.5|-28||||
  11 NX-Metal-1-Metal-2-Con|contact@4||0|-28||||
  12 NMetal-1-Polysilicon-Con|contact@5||-17.5|62||5.2||
  13 NMetal-1-Polysilicon-Con|contact@6||-8.5|62||5.2||
  14 IlatchPartsK:latchAmp20;1{lay}|latchAmp@0||27|0|||D5G4;
  15 NPolysilicon-Pin|pin@10||-17|59.4||||
  16 NPolysilicon-Pin|pin@11||-9|59.4||||
  17 NMetal-1-Pin|pin@12||-17.5|63||||
  18 NMetal-1-Pin|pin@13||-8.5|63||||
  19 Iraw2inLatchF;1{lay}|raw2inLa@0||-8|0|||D5G4;
  20 Ametal-2|net@0|||S0|latchAmp@0|gnd|19|0|raw2inLa@0|gnd_1|19|0
  21 Ametal-2|net@1|||S0|latchAmp@0|vdd_2|19|50|raw2inLa@0|vdd_3|19|50
  22 Ametal-2|net@2|||S0|latchAmp@0|vdd|19|-50|raw2inLa@0|vdd_4|19|-50
  23 Ametal-1|net@8|||S900|latchAmp@0|in|22.5|-25|contact@1||22.5|-28
  24 Ametal-2|net@16|||S0|contact@1||22.5|-28|contact@4||0|-28
  25 Ametal-1|net@17|||S900|raw2inLa@0|out[F]|0|-12.5|contact@4||0|-28
  26 APolysilicon|net@23|||S1800|contact@5||-17.5|59.4|pin@10||-17|59.4
  27 APolysilicon|net@24|||S900|pin@10||-17|59.4|raw2inLa@0|hcl[A]|-17|58.5
  28 APolysilicon|net@25|||S0|contact@6||-8.5|59.4|pin@11||-9|59.4
  29 APolysilicon|net@26|||S900|pin@11||-9|59.4|raw2inLa@0|hcl[B]|-9|58.5
  30 Ametal-1|net@28|||S900|contact@5||-17.5|63|pin@12||-17.5|63
  31 Ametal-1|net@29|||S900|contact@6||-8.5|63|pin@13||-8.5|63
  32 Egnd||D5G2;|raw2inLa@0|gnd|G
  33 Egnd_1||D5G2;|latchAmp@0|gnd_1|G
  34 Ehcl[A]||D5FLeave alone;G2;|pin@12||I
  35 Ehcl[B]||D5FLeave alone;G2;|pin@13||I
  36 EinA[1]||D5FLeave alone;G2;|raw2inLa@0|inA[1]|I
  37 EinB[1]||D5G2;|raw2inLa@0|inB[1]|I
  38 Eout[1]||D5G2;|latchAmp@0|out[1]|O
  39 Evdd||D5G2;|raw2inLa@0|vdd|P
  40 Evdd_1||D5G2;|latchAmp@0|vdd_1|P
  41 Evdd_2||D5G2;|raw2inLa@0|vdd_2|P
  42 Evdd_3||D5G2;|latchAmp@0|vdd_3|O
  43 X