chips/marina/electric/latchesK.delib/latch2in60Cm2dn.lay

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 # Cell latch2in60Cm2dn;2{lay}
   8 Clatch2in60Cm2dn;2{lay}|latch2in60C|cmos90|1194627475361|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241982205540
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NX-Metal-1-Metal-2-Con|contact@1||-37|-28||||
  11 NX-Metal-1-Metal-2-Con|contact@2||-6|-28||||
  12 NX-Metal-1-Metal-2-Con|contact@3||64|-40||||
  13 NX-Metal-1-Metal-2-Con|contact@4||-31.5|28||||
  14 NX-Metal-1-Metal-2-Con|contact@5||-58.5|22||||
  15 Iraw2inLatchF;1{lay}|hi2inLat@1||-45|0|||D5G4;
  16 IlatchPartsK:latchAmp60Cm1;1{lay}|latchAmp@1||40|0|||D5G4;
  17 NMetal-2-Pin|pin@0||58|-40||||
  18 NMetal-2-Pin|pin@1||-52.5|22||||
  19 NMetal-2-Pin|pin@2||-37.5|28||||
  20 NMetal-1-Pin|pin@3||-58.5|25||||
  21 Ametal-2|net@14||6.2|S0|latchAmp@1|vdd_1|-13.5|50|hi2inLat@1|vdd_3|-18|50
  22 Ametal-2|net@18|||S1800|contact@1||-37|-28|contact@2||-6|-28
  23 Ametal-1|net@23|||S900|latchAmp@1|in|-6|-24|contact@2||-6|-28
  24 Ametal-1|net@33|||S2700|contact@1||-37|-28|hi2inLat@1|out[F]|-37|-12.5
  25 Ametal-2|net@40||6.2|S1800|hi2inLat@1|gnd_1|-18|0|latchAmp@1|gnd|-13.5|0
  26 Ametal-2|net@41||6.2|S0|latchAmp@1|vdd|-13.5|-50|hi2inLat@1|vdd_4|-18|-50
  27 Ametal-2|net@42|||S1800|pin@0||58|-40|contact@3||64|-40
  28 Ametal-1|net@43|||S900|latchAmp@1|out[1]|64|13|contact@3||64|-40
  29 Ametal-2|net@44|||S1800|pin@2||-37.5|28|contact@4||-31.5|28
  30 Ametal-1|net@45|||S2700|hi2inLat@1|inB[1]|-31.5|-7|contact@4||-31.5|28
  31 Ametal-2|net@46|||S0|pin@1||-52.5|22|contact@5||-58.5|22
  32 Ametal-1|net@47|||S2700|hi2inLat@1|inA[1]|-58.5|-7|contact@5||-58.5|22
  33 Ametal-1|net@48||0.4|S2700|contact@5||-58.5|22|pin@3||-58.5|25
  34 Egnd||D5G2;|hi2inLat@1|gnd|G
  35 Egnd_1||D5G2;|latchAmp@1|gnd_1|G
  36 Ehcl[A]||D5G2;|hi2inLat@1|hcl[A]|I
  37 Ehcl[B]||D5G2;|hi2inLat@1|hcl[B]|I
  38 EinA[1]||D5G2;|pin@1||I
  39 EinB[1]||D5G2;|pin@2||I
  40 EoutS[1]||D5G2;|pin@0||O
  41 Evdd||D5G2;|hi2inLat@1|vdd|P
  42 Evdd_2||D5G2;|hi2inLat@1|vdd_2|P
  43 Evdd_3||D5G2;|latchAmp@1|vdd_2|P
  44 Evdd_4||D5G2;|latchAmp@1|vdd_3|P
  45 X