chips/marina/electric/latchesK.delib/latch3in30Bmc.sch

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell latch3in30Bmc;1{sch}
  10 Clatch3in30Bmc;1{sch}||schematic|1194187081843|1207845507178|
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||-21|2||||
  13 NOff-Page|conn@1||-21|9||||
  14 NOff-Page|conn@3||-3|-9|||X|
  15 NOff-Page|conn@4||27|0||||
  16 NOff-Page|conn@5||-21|-9||||
  17 NOff-Page|conn@6||-21|-2||||
  18 Iraw3inLatchTmcLO;1{ic}|hi2inLat@0||-9|0|||D5G4;
  19 IredFive:invLT;1{ic}|invLT@0||6|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  20 IredFive:inv;1{ic}|invLT@1||18|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  21 Ilatch3in30Bmc;1{ic}|latch2in@0||33|15|||D5G4;
  22 Ngeneric:Invisible-Pin|pin@0||0|15.5|||||ART_message(D5FLeave alone;G3;)Sies 9 April 2008
  23 Ngeneric:Invisible-Pin|pin@1||0|22.5|||||ART_message(D5FLeave alone;G4;)S[two input latch with two amplifiers,and Master Clear]
  24 Ngeneric:Invisible-Pin|pin@2||0|31.5|||||ART_message(D5G6;)Slatch3in30Bmc
  25 NWire_Pin|pin@8||-10|9||||
  26 NWire_Pin|pin@10||-8|-9||||
  27 NWire_Pin|pin@13||-10|-9||||
  28 NWire_Pin|pin@14||-15|2||||
  29 NWire_Pin|pin@15||-15|1||||
  30 NWire_Pin|pin@16||-15|-2||||
  31 NWire_Pin|pin@17||-15|-1||||
  32 IorangeTSMC090nm:wire90;1{ic}|wire90@0||0|0|||D0G4;|ATTR_L(D5G1;PUD)D342.1|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  33 IorangeTSMC090nm:wire90;1{ic}|wire90@1||12|0|||D0G4;|ATTR_L(D5G1;PUD)D329.19999999999993|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  34 Awire|net@8|||1800|conn@1|y|-19|9|pin@8||-10|9
  35 Awire|net@14|||0|wire90@0|a|-2.5|0|hi2inLat@0|out[T]|-5|0
  36 Awire|net@15|||0|invLT@0|in|3.5|0|wire90@0|b|2.5|0
  37 Awire|net@16|||1800|wire90@1|b|14.5|0|invLT@1|in|15.5|0
  38 Awire|net@18|||0|wire90@1|a|9.5|0|invLT@0|out|8.5|0
  39 Awire|net@25|||0|conn@4|a|25|0|invLT@1|out|20.5|0
  40 Awire|net@35|||0|conn@3|y|-5|-9|pin@10||-8|-9
  41 Awire|net@36|||900|hi2inLat@0|hcl[C]|-8|-3|pin@10||-8|-9
  42 Awire|net@39|||900|pin@8||-10|9|hi2inLat@0|hcl[A]|-10|3
  43 Awire|net@42|||2700|pin@13||-10|-9|hi2inLat@0|hcl[B]|-10|-3
  44 Awire|net@43|||1800|conn@0|y|-19|2|pin@14||-15|2
  45 Awire|net@44|||900|pin@14||-15|2|pin@15||-15|1
  46 Awire|net@45|||1800|pin@15||-15|1|hi2inLat@0|inA[1]|-11|1
  47 Awire|net@46|||1800|conn@6|y|-19|-2|pin@16||-15|-2
  48 Awire|net@47|||2700|pin@16||-15|-2|pin@17||-15|-1
  49 Awire|net@48|||1800|pin@17||-15|-1|hi2inLat@0|inB[1]|-11|-1
  50 Awire|net@49|||1800|conn@5|y|-19|-9|pin@13||-10|-9
  51 Ehcl|hcl[A]|D4G2;|conn@1|a|I
  52 Ehcl[A_1]|hcl[B]|D4G2;|conn@5|a|I
  53 EinA[1]||D4G2;|conn@0|a|I
  54 EinA[2]|inB[1]|D4G2;|conn@6|a|I
  55 Emc||D4G2;|conn@3|a|I
  56 Eout[1]||D6G2;|conn@4|y|O
  57 X