chips/marina/electric/latchesK.delib/mlatThru5.sch

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell mlatThru5;1{sch}
  10 CmlatThru5;1{sch}||schematic|1214214085210|1214305976720|
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||33|0||||
  13 NOff-Page|conn@1||-15|-18|||YRRR|
  14 NOff-Page|conn@2||0|-18|||R|
  15 IredFive:invLT;1{ic}|invLT@0||21|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  16 ImlatThru5;1{ic}|mlatThru@1||27|18.5|||D5G4;
  17 IredFive:nms2b;1{ic}|nms2@0||9|-9|X||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S2.5
  18 IredFive:nms2b;1{ic}|nms2@1||-9|-9|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-0.5;)I100|ATTR_X(D5G1.5;NOJPX-2.25;Y1.5;)S2.5
  19 Ngeneric:Invisible-Pin|pin@0||-0.5|24|||||ART_message(D5G3;)Sies 23 June 2008
  20 Ngeneric:Invisible-Pin|pin@1||-0.5|28|||||ART_message(D5G4;)Snon-inverting mux latch
  21 Ngeneric:Invisible-Pin|pin@2||-0.5|33|||||ART_message(D5G6;)SmlatThru5
  22 NWire_Pin|pin@3||-15|9||||
  23 NWire_Pin|pin@4||-9|0||||
  24 NWire_Pin|pin@5||-15|-9||||
  25 NWire_Pin|pin@6||-2|-5||||
  26 NWire_Pin|pin@7||-2|5||||
  27 NWire_Pin|pin@8||27|-9||||
  28 NWire_Pin|pin@9||27|9||||
  29 NWire_Pin|pin@10||-2|-12.5||||
  30 NWire_Pin|pin@11||-2|11.5||||
  31 NWire_Pin|pin@12||9|0||||
  32 NWire_Pin|pin@13||-2|-2||||
  33 NWire_Pin|pin@14||2|2||||
  34 NWire_Pin|pin@15||2|-2|||X|
  35 NWire_Pin|pin@16||-2|2|||X|
  36 NWire_Pin|pin@17||27|0||||
  37 NWire_Pin|pin@18||2|5||||
  38 NWire_Pin|pin@19||2|-5||||
  39 Ngeneric:Invisible-Pin|pin@20||-14.5|19|||||ART_message(D3G2;)Slatch is transparent when c is true
  40 IredFive:pms2;1{ic}|pms2@0||9|9|X||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX2.25;Y1;)S1
  41 IredFive:pms2;1{ic}|pms2@1||-9|9|||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX2.25;Y1;)S2.5
  42 IorangeTSMC090nm:wire90;1{ic}|wire90@0||14.5|0|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D205.89999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  43 Awire|c[F]|D5G2;||2700|pin@7||-2|5|pin@11||-2|11.5
  44 Awire|c[T]|D5G2;||900|pin@6||-2|-5|pin@10||-2|-12.5
  45 Awire|net@0|||0|invLT@0|in|18.5|0|wire90@0|b|17|0
  46 Awire|net@1|||2250|pin@13||-2|-2|pin@14||2|2
  47 Awire|net@2|||3150|pin@15||2|-2|pin@16||-2|2
  48 Awire|net@3|||0|pin@17||27|0|invLT@0|out|23.5|0
  49 Awire|net@4|||2700|pin@8||27|-9|pin@17||27|0
  50 Awire|net@5|||2700|pin@12||9|0|pms2@0|d|9|3
  51 Awire|net@6|||2700|pin@14||2|2|pin@18||2|5
  52 Awire|net@7|||1800|pin@18||2|5|pms2@0|g2|6|5
  53 Awire|net@8|||900|pin@15||2|-2|pin@19||2|-5
  54 Awire|net@9|||1800|pin@19||2|-5|nms2@0|g2|6|-5
  55 Awire|net@10|||1800|pin@3||-15|9|pms2@1|g|-12|9
  56 Awire|net@11|||900|pin@4||-9|0|nms2@1|d|-9|-3
  57 Awire|net@12|||900|pms2@1|d|-9|3|pin@4||-9|0
  58 Awire|net@13|||0|pin@12||9|0|pin@4||-9|0
  59 Awire|net@14|||2700|pin@16||-2|2|pin@7||-2|5
  60 Awire|net@15|||2700|pin@5||-15|-9|pin@3||-15|9
  61 Awire|net@16|||2700|conn@1|y|-15|-16|pin@5||-15|-9
  62 Awire|net@17|||0|nms2@1|g|-12|-9|pin@5||-15|-9
  63 Awire|net@18|||1800|nms2@1|g2|-6|-5|pin@6||-2|-5
  64 Awire|net@19|||2700|pin@6||-2|-5|pin@13||-2|-2
  65 Awire|net@20|||0|pin@7||-2|5|pms2@1|g2|-6|5
  66 Awire|net@21|||900|pin@9||27|9|pin@17||27|0
  67 Awire|net@22|||1800|nms2@0|g|12|-9|pin@8||27|-9
  68 Awire|net@23|||2700|nms2@0|d|9|-3|pin@12||9|0
  69 Awire|net@24|||1800|pms2@0|g|12|9|pin@9||27|9
  70 Awire|net@25|||0|wire90@0|a|12|0|pin@12||9|0
  71 Awire|net@26|||0|conn@0|a|31|0|pin@17||27|0
  72 Ec[T,F]||D4G2;|conn@2|a|I
  73 Ein[1]||D4G2;|conn@1|a|I
  74 Eout[1]||D6G2;|conn@0|y|O
  75 X