chips/marina/electric/latchesK.delib/raw1inLatchT.sch

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 LorangeTSMC090nm|orangeTSMC090nm
   8
   9 # Cell raw1inLatchT;1{sch}
  10 Craw1inLatchT;1{sch}||schematic|1194181042341|1206032620336|
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||9|-1||||
  13 NOff-Page|conn@1||-18|6||||
  14 NOff-Page|conn@2||-18|12||||
  15 Iraw1inLatchT;1{ic}|hi2inLat@0||11|13|||D5G4;
  16 IlatchPartsK:latchKeep;1{ic}|latchFlo@0||0|-1|||D5G4;
  17 IlatchPartsK:latchPointT;1{ic}|latchPoi@0||-8|6|||D5G4;
  18 NWire_Pin|pin@6||-4|5||||
  19 NWire_Pin|pin@8||4|7||||
  20 NWire_Pin|pin@10||4|-1||||
  21 Ngeneric:Invisible-Pin|pin@13||0|28|||||ART_message(D5G6;)Sraw1inLatchT
  22 Ngeneric:Invisible-Pin|pin@14||0|19|||||ART_message(D5G3;)Sies 4 November 2007
  23 Ngeneric:Invisible-Pin|pin@15||0|23|||||ART_message(D5G4;)STRUE output latch
  24 NWire_Pin|pin@16||-10|12||||
  25 NWire_Pin|pin@17||-4|2||||
  26 NWire_Pin|pin@18||-13|2||||
  27 NWire_Pin|pin@19||-13|-1||||
  28 IorangeTSMC090nm:wire90;1{ic}|wire90@0||-8|-1|||D0G4;|ATTR_L(D5G1;PUD)D180.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  29 Awire|net@7|||0|pin@6||-4|5|latchPoi@0|x[F]|-5|5
  30 Awire|net@11|||1800|latchPoi@0|x[T]|3|7|pin@8||4|7
  31 Awire|net@12|||900|pin@8||4|7|pin@10||4|-1
  32 Awire|net@19|||1800|latchFlo@0|out[B]|2|-1|pin@10||4|-1
  33 Awire|net@20|||0|conn@0|a|7|-1|pin@10||4|-1
  34 Awire|net@21|||1800|conn@1|y|-16|6|latchPoi@0|in[1]|-11|6
  35 Awire|net@22|||1800|conn@2|y|-16|12|pin@16||-10|12
  36 Awire|net@23|||900|pin@16||-10|12|latchPoi@0|hcl|-10|9
  37 Awire|net@25|||2700|pin@17||-4|2|pin@6||-4|5
  38 Awire|net@26|||0|pin@17||-4|2|pin@18||-13|2
  39 Awire|net@27|||900|pin@18||-13|2|pin@19||-13|-1
  40 Awire|net@28|||1800|pin@19||-13|-1|wire90@0|a|-10.5|-1
  41 Awire|net@29|||0|latchFlo@0|out[s]|-2|-1|wire90@0|b|-5.5|-1
  42 Ehcl[A]||D4G2;|conn@2|a|I
  43 EinA[1]||D4G2;|conn@1|a|I
  44 Eout[T]||D6G2;|conn@0|y|O
  45 X