chips/marina/electric/latchesK.delib/raw2inLatchFmc.sch

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 LorangeTSMC090nm|orangeTSMC090nm
   8
   9 # Cell raw2inLatchFmc;1{sch}
  10 Craw2inLatchFmc;1{sch}||schematic|1194181042341|1205533358954|
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||9|0||||
  13 NOff-Page|conn@1||-18|6||||
  14 NOff-Page|conn@2||-18|12||||
  15 NOff-Page|conn@4||-18|-12||||
  16 Iraw2inLatchFmc;1{ic}|hi2inLat@0||12.5|11.5|||D5G4;
  17 IlatchPartsK:latchKeep;1{ic}|latchKee@0||0|0|||D5G4;
  18 IlatchPartsK:latchPointF;1{ic}|latchPoi@0||-8|6|||D5G4;
  19 IlatchPartsK:latchPointFmcHI;1{ic}|latchPoi@1||-8|-6|Y||D5G4;
  20 Ngeneric:Invisible-Pin|pin@13||1.5|28|||||ART_message(D5G6;)Sraw2inLatchFmc
  21 Ngeneric:Invisible-Pin|pin@14||0.5|19|||||ART_message(D5G3;)Sies 10 November 2007
  22 Ngeneric:Invisible-Pin|pin@15||-0.5|23|||||ART_message(D5G4;)SINVERTING output latch w/HI mc
  23 NWire_Pin|pin@16||-10|12||||
  24 NWire_Pin|pin@17||-10|-12||||
  25 NWire_Pin|pin@18||4|7||||
  26 NWire_Pin|pin@19||4|-7||||
  27 NWire_Pin|pin@20||4|0||||
  28 NWire_Pin|pin@23||-4|5||||
  29 NWire_Pin|pin@24||-4|-5||||
  30 NWire_Pin|pin@25||-4|2||||
  31 NWire_Pin|pin@26||-12|2||||
  32 NWire_Pin|pin@27||-12|-2||||
  33 NWire_Pin|pin@28||-4|-2||||
  34 NWire_Pin|pin@29||-12|0||||
  35 IorangeTSMC090nm:wire90;1{ic}|wire90@0||-8|0|||D0G4;|ATTR_L(D5G1;PUD)D145.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  36 Awire|net@21|||1800|conn@1|y|-16|6|latchPoi@0|in[1]|-11|6
  37 Awire|net@22|||1800|conn@2|y|-16|12|pin@16||-10|12
  38 Awire|net@23|||900|pin@16||-10|12|latchPoi@0|hcl|-10|9
  39 Awire|net@25|||1800|conn@4|y|-16|-12|pin@17||-10|-12
  40 Awire|net@26|||2700|pin@17||-10|-12|latchPoi@1|mc|-10|-9
  41 Awire|net@37|||1800|latchPoi@0|x[F]|3|7|pin@18||4|7
  42 Awire|net@38|||900|pin@20||4|0|pin@19||4|-7
  43 Awire|net@39|||0|pin@19||4|-7|latchPoi@1|x[F]|3|-7
  44 Awire|net@40|||900|pin@18||4|7|pin@20||4|0
  45 Awire|net@41|||1800|pin@20||4|0|conn@0|a|7|0
  46 Awire|net@45|||0|pin@23||-4|5|latchPoi@0|x[T]|-5|5
  47 Awire|net@46|||900|pin@28||-4|-2|pin@24||-4|-5
  48 Awire|net@47|||0|pin@24||-4|-5|latchPoi@1|x[T]|-5|-5
  49 Awire|net@48|||2700|pin@25||-4|2|pin@23||-4|5
  50 Awire|net@53|||0|pin@20||4|0|latchKee@0|out[B]|2|0
  51 Awire|net@56|||0|pin@25||-4|2|pin@26||-12|2
  52 Awire|net@57|||900|pin@29||-12|0|pin@27||-12|-2
  53 Awire|net@59|||1800|pin@27||-12|-2|pin@28||-4|-2
  54 Awire|net@60|||900|pin@26||-12|2|pin@29||-12|0
  55 Awire|net@61|||1800|pin@29||-12|0|wire90@0|a|-10.5|0
  56 Awire|net@63|||0|latchKee@0|out[s]|-2|0|wire90@0|b|-5.5|0
  57 Ehcl||D4G2;|conn@2|a|I
  58 EinA[1]||D4G2;|conn@1|a|I
  59 Emc||D4G2;|conn@4|a|I
  60 Eout[F]||D6G2;|conn@0|y|O
  61 X