chips/marina/electric/latchesK.delib/raw2inLatchT.sch

   1 HlatchesK|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchPartsK|latchPartsK
   6
   7 LorangeTSMC090nm|orangeTSMC090nm
   8
   9 # Cell raw2inLatchT;1{sch}
  10 Craw2inLatchT;1{sch}||schematic|1194181042341|1205533536139|
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||9|0||||
  13 NOff-Page|conn@1||-18|6||||
  14 NOff-Page|conn@2||-18|12||||
  15 NOff-Page|conn@3||-18|-6|||XRR|
  16 NOff-Page|conn@4||-18|-12||||
  17 Iraw2inLatchT;1{ic}|hi2inLat@0||11|13|||D5G4;
  18 IlatchPartsK:latchKeep;1{ic}|latchFlo@0||0|0|||D5G4;
  19 IlatchPartsK:latchPointT;1{ic}|latchPoi@0||-8|6|||D5G4;
  20 IlatchPartsK:latchPointT;1{ic}|latchPoi@1||-8|-6|Y||D5G4;
  21 NWire_Pin|pin@4||-4|0||||
  22 NWire_Pin|pin@6||-4|5||||
  23 NWire_Pin|pin@8||4|7||||
  24 NWire_Pin|pin@10||4|0||||
  25 NWire_Pin|pin@11||-4|-5||||
  26 NWire_Pin|pin@12||4|-7||||
  27 Ngeneric:Invisible-Pin|pin@13||1.5|28|||||ART_message(D5G6;)Sraw2inLatchT
  28 Ngeneric:Invisible-Pin|pin@14||0.5|19|||||ART_message(D5G3;)Sies 4 November 2007
  29 Ngeneric:Invisible-Pin|pin@15||-0.5|23|||||ART_message(D5G4;)STRUE output latch
  30 NWire_Pin|pin@16||-10|12||||
  31 NWire_Pin|pin@17||-10|-12||||
  32 IorangeTSMC090nm:wire90;1{ic}|wire90@0||-9|0|||D0G4;|ATTR_L(D5G1;PUD)D180.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  33 Awire|net@4|||0|latchFlo@0|out[s]|-2|0|pin@4||-4|0
  34 Awire|net@7|||0|pin@6||-4|5|latchPoi@0|x[F]|-5|5
  35 Awire|net@8|||2700|pin@4||-4|0|pin@6||-4|5
  36 Awire|net@11|||1800|latchPoi@0|x[T]|3|7|pin@8||4|7
  37 Awire|net@12|||900|pin@8||4|7|pin@10||4|0
  38 Awire|net@15|||900|pin@4||-4|0|pin@11||-4|-5
  39 Awire|net@16|||0|pin@11||-4|-5|latchPoi@1|x[F]|-5|-5
  40 Awire|net@17|||900|pin@10||4|0|pin@12||4|-7
  41 Awire|net@18|||0|pin@12||4|-7|latchPoi@1|x[T]|3|-7
  42 Awire|net@19|||1800|latchFlo@0|out[B]|2|0|pin@10||4|0
  43 Awire|net@20|||0|conn@0|a|7|0|pin@10||4|0
  44 Awire|net@21|||1800|conn@1|y|-16|6|latchPoi@0|in[1]|-11|6
  45 Awire|net@22|||1800|conn@2|y|-16|12|pin@16||-10|12
  46 Awire|net@23|||900|pin@16||-10|12|latchPoi@0|hcl|-10|9
  47 Awire|net@24|||1800|conn@3|y|-16|-6|latchPoi@1|in[1]|-11|-6
  48 Awire|net@25|||1800|conn@4|y|-16|-12|pin@17||-10|-12
  49 Awire|net@26|||2700|pin@17||-10|-12|latchPoi@1|hcl|-10|-9
  50 Awire|net@27|||1800|wire90@0|b|-6.5|0|pin@4||-4|0
  51 Ehcl[A]||D4G2;|conn@2|a|I
  52 Ehcl[B]||D4G2;|conn@4|a|I
  53 EinA[1]||D4G2;|conn@1|a|I
  54 EinB[1]||D4G2;|conn@3|a|I
  55 Eout[T]||D6G2;|conn@0|y|O
  56 X