7 LorangeTSMC090nm|orangeTSMC090nm
11 # Cell ohPredPred;1{sch}
12 CohPredPred;1{sch}||schematic|1231956735131|1239968060363|
13 Ngeneric:Facet-Center|art@0||0|0||||AV
14 NOff-Page|conn@0||-26|22||||
15 NOff-Page|conn@2||21|12|||R|
16 NOff-Page|conn@3||-12|15|||R|
17 NOff-Page|conn@4||27|12|||R|
18 NOff-Page|conn@8||-14|-1|||XRR|
19 NOff-Page|conn@9||3|20|||XR|
20 NOff-Page|conn@10||-31|14||||
21 NOff-Page|conn@12||12|20|||XR|
22 IredFive:inv;1{ic}|inv@0||3|13|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
23 IredFive:inv;1{ic}|inv@2||-1|-1|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
24 IredFive:invI;2{ic}|invI@0||12|4|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
25 IredFive:invI;2{ic}|invI@4||-3|37|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
26 IredFive:invI;2{ic}|invI@5||-3|48|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
27 IredFive:nor2_sy;1{ic}|nor2_sy@5||-18|48|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.25;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
28 IredFive:nor2_sy;1{ic}|nor2_sy@6||-18|37|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.25;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
29 IohPredPred;1{ic}|ohPredPr@1||33|34|||D5G4;
30 IohSRxor6x12;1{ic}|ohSRxor6@1||24|0|XR||D5G4;
31 Ngeneric:Invisible-Pin|pin@0||-0.5|58.5|||||ART_message(D5G2;)SThis is the predecessor part of the Predicate stage
32 Ngeneric:Invisible-Pin|pin@1||-1.5|67|||||ART_message(D5G5;)SohPredPred
33 Ngeneric:Invisible-Pin|pin@2||-1|63|||||ART_message(D5G3;)Sies 14 January 2009
34 NWire_Pin|pin@3||-12|20||||
35 NBus_Pin|pin@18||28|-6|-1|-1||
36 NBus_Pin|pin@19||20|-6|-1|-1||
37 NBus_Pin|pin@20||16|-6|-1|-1||
38 NBus_Pin|pin@21||16|-10|-1|-1||
39 NBus_Pin|pin@22||32|-6|-1|-1||
40 NBus_Pin|pin@23||32|-10|-1|-1||
41 NWire_Pin|pin@29||12|9|||X|
42 NWire_Pin|pin@30||3|9|||X|
43 NWire_Pin|pin@31||12|-1||||
44 NWire_Pin|pin@32||-6|24||||
45 NBus_Pin|pin@35||24|-7|-1|-1||
46 NWire_Pin|pin@37||-24|36||||
47 NWire_Pin|pin@38||-24|33||||
48 NWire_Pin|pin@39||-27|38||||
49 NWire_Pin|pin@40||-27|41||||
50 NWire_Pin|pin@41||9|37|||X|
51 NWire_Pin|pin@42||9|33|||X|
52 Ngeneric:Invisible-Pin|pin@43||-51.5|41.5|||||ART_message(D3G2;)S[scan report of an,"example m1cate,","m1cate[1][T,F].","Flag[A,B] reported",by flag stage.,"Flag[D] reported",by on deck stage.]
53 NWire_Pin|pin@44||-24|47||||
54 NWire_Pin|pin@45||-24|44||||
55 NWire_Pin|pin@46||-27|49||||
56 NWire_Pin|pin@47||-27|52||||
57 NWire_Pin|pin@48||9|48|||X|
58 NWire_Pin|pin@49||9|44|||X|
59 NWire_Pin|pin@51||-6|-1||||
60 IdriversM:predDri20wMC;1{ic}|pp[1:12]|D5G3;Y6;|-17|22|X||D5G4;
61 IorangeTSMC090nm:wire90;1{ic}|wire90@1||7|-1|||D0G4;|ATTR_L(D5G1;PUD)D625.1000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
62 IorangeTSMC090nm:wire90;1{ic}|wire90@3||7|9|X||D0G4;|ATTR_L(D5G1;PUD)D142.60000000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
63 IorangeTSMC090nm:wire90;1{ic}|wire90@4||-11|37|||D0G4;|ATTR_L(D5G1;PUD)D215.39999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
64 IorangeTSMC090nm:wire90;1{ic}|wire90@5||-11|48|||D0G4;|ATTR_L(D5G1;PUD)D215.40000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
65 Abus|flag[A,B,D][set,clr]|D5G2;|-0.5|IJ900|ohSRxor6@1|flag[1:3][set,clr]|24|-3|pin@35||24|-7
66 Awire|flag[A][clr]|D5G2;||900|pin@44||-24|47|pin@45||-24|44
67 Awire|flag[A][set]|D5G2;||2700|pin@46||-27|49|pin@47||-27|52
68 Abus|m1cate[1:6][F]|D5G2;|-0.5|IJ900|pin@22||32|-6|pin@23||32|-10
69 Abus|m1cate[1:6][T]|D5G2;|-0.5|IJ900|pin@20||16|-6|pin@21||16|-10
70 Awire|m1cate[1][F]|D5G2;||900|pin@37||-24|36|pin@38||-24|33
71 Awire|m1cate[1][T]|D5G2;||2700|pin@39||-27|38|pin@40||-27|41
72 Abus|net@0||-0.5|IJ0|pp[1:12]|pred|-20|22|conn@0|y|-24|22
73 Awire|net@1|||1800|pp[1:12]|mc|-14|20|pin@3||-12|20
74 Awire|net@8|||1800|pp[1:12]|in|-14|24|pin@32||-6|24
75 Awire|net@18|||0|ohSRxor6@1|resetLO|17|-1|pin@31||12|-1
76 Awire|net@19|||900|conn@2|a|21|10|ohSRxor6@1|any|21|7
77 Awire|net@20|||900|conn@4|a|27|10|ohSRxor6@1|all|27|7
78 Awire|net@23|||2700|conn@3|y|-12|17|pin@3||-12|20
79 Abus|net@31||-0.5|IJ900|ohSRxor6@1|in[1:6][F]|28|-3|pin@18||28|-6
80 Abus|net@32||-0.5|IJ900|ohSRxor6@1|in[1:6][T]|20|-3|pin@19||20|-6
81 Abus|net@33||-0.5|IJ0|pin@19||20|-6|pin@20||16|-6
82 Abus|net@35||-0.5|IJ1800|pin@18||28|-6|pin@22||32|-6
83 Awire|net@49|||2700|invI@0|out|12|6.5|pin@29||12|9
84 Awire|net@50|||0|pin@29||12|9|wire90@3|a|9.5|9
85 Awire|net@51|||900|inv@0|in|3|10.5|pin@30||3|9
86 Awire|net@52|||1800|pin@30||3|9|wire90@3|b|4.5|9
87 Awire|net@53|||900|conn@9|a|3|18|inv@0|out|3|15.5
88 Awire|net@54|||1800|inv@2|out|1.5|-1|wire90@1|a|4.5|-1
89 Awire|net@55|||0|pin@31||12|-1|wire90@1|b|9.5|-1
90 Awire|net@56|||900|invI@0|in|12|1.5|pin@31||12|-1
91 Awire|net@61|||900|pin@32||-6|24|pin@51||-6|-1
92 Awire|net@62|||0|wire90@4|a|-13.5|37|nor2_sy@6|out|-15.5|37
93 Awire|net@63|||0|nor2_sy@6|ina|-20.5|36|pin@37||-24|36
94 Awire|net@64|||0|nor2_sy@6|inb|-20.5|38|pin@39||-27|38
95 Awire|net@65|||1800|invI@4|out|-0.5|37|pin@41||9|37
96 Awire|net@66|||0|invI@4|in|-5.5|37|wire90@4|b|-8.5|37
97 Awire|net@67|||0|wire90@5|a|-13.5|48|nor2_sy@5|out|-15.5|48
98 Awire|net@68|||0|nor2_sy@5|ina|-20.5|47|pin@44||-24|47
99 Awire|net@69|||0|nor2_sy@5|inb|-20.5|49|pin@46||-27|49
100 Awire|net@70|||1800|invI@5|out|-0.5|48|pin@48||9|48
101 Awire|net@71|||0|invI@5|in|-5.5|48|wire90@5|b|-8.5|48
102 Awire|net@77|||0|pin@51||-6|-1|conn@8|y|-12|-1
103 Awire|net@78|||0|inv@2|in|-3.5|-1|pin@51||-6|-1
104 Awire|s[1]|D5G2;||900|pin@41||9|37|pin@42||9|33
105 Awire|s[2]|D5G2;||900|pin@48||9|48|pin@49||9|44
106 Eskip|any|D6G2;|conn@2|y|O
107 Edo||D6G2;|conn@4|y|O
108 Ehit[do]|fire[both]|D4G2;|conn@8|a|I
109 Eflag[A,B][set,clr]|flag[A,B,D][set,clr]|D4G2;|conn@10|a|I
110 Em1cate[1:6][T,F]||D4G2;|conn@0|a|I
111 Emc||D4G2;|conn@3|a|I
112 EresetLO||D6G2;|conn@9|y|O
113 Es[1,2]||D6G2;|conn@12|y|O
projects / fleet.git / blob