chips/marina/electric/purpleFive.delib/inv2iHT.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell inv2iHT;1{sch}
   8 Cinv2iHT;1{sch}||schematic|1021415734000|1159375639594||ATTR_Delay(D5G1;HNPX-11;Y-7.5;)I100|ATTR_LEGATE(D5G1;HNPTX-11;Y-12.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-11;Y-8.5;)I-1|ATTR_X(D5G1;HNOJPX-11;Y-6.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-11;Y-9.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-11;Y-10.5;)Sstrong1|ATTR_su(D5G1;HNPTX-11;Y-11.5;)I-1|prototype_center()I[0,0]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||12|0||||
  11 NOff-Page|conn@1||-10|1|||Y|
  12 NOff-Page|conn@2||-10|-1|||Y|
  13 IredFive:inv2iHT;1{ic}|inv2iHT@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
  14 Iinv2iHT;1{ic}|inv2iHT@1||23|12.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
  15 Ngeneric:Invisible-Pin|pin@0||13|-11|||||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
  16 Ngeneric:Invisible-Pin|pin@1||-3.5|13.5|||||ART_message(D5G2;)S[P to N width ratio is 4 to 1]
  17 Ngeneric:Invisible-Pin|pin@2||-3.5|20.5|||||ART_message(D5G6;)S[inv2iHT]
  18 Ngeneric:Invisible-Pin|pin@3||-3.5|15.5|||||ART_message(D5G2;)S[two-input HI-threshold inverter]
  19 Awire|net@0|||0|inv2iHT@0|in[p]|-2.5|1|conn@1|y|-8|1
  20 Awire|net@1|||0|inv2iHT@0|in[n]|-2.5|-1|conn@2|y|-8|-1
  21 Awire|net@2|||0|conn@0|a|10|0|inv2iHT@0|out|2.5|0
  22 Ein[n]||D5G2;|conn@2|a|I|ATTR_le(D5G1;NX0.5;Y2;)F0.33
  23 Ein[p]||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-1.5;)F1.33
  24 Eout||D5G2;|conn@0|y|O|ATTR_le(D5G1;NY2;)F1.67
  25 X