chips/marina/electric/purpleFive.delib/inv2iK.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell inv2iK;1{sch}
   8 Cinv2iK;1{sch}||schematic|1021415734000|1159376928498||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-10.5|-1|||Y|
  11 NOff-Page|conn@1||-10.5|1|||Y|
  12 NOff-Page|conn@2||24|0||||
  13 IredFive:inv2i;1{ic}|inv2i@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
  14 Iinv2iK;1{ic}|inv2iK@0||24|17|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
  15 IredFive:invK;1{ic}|invK@0||8|6|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X/20.|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1
  16 IredFive:invK;1{ic}|invK@1||14.5|6|YR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X/20.|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1
  17 NWire_Pin|pin@0||8|10.5||||
  18 NWire_Pin|pin@1||14.5|10.5||||
  19 NWire_Pin|pin@2||14.5|0||||
  20 NWire_Pin|pin@3||8|0||||
  21 Ngeneric:Invisible-Pin|pin@4||11|-5|||||SIM_spice_card(D6G1;)S[.ic v(out) 'vhi']
  22 Ngeneric:Invisible-Pin|pin@5||-4|20|||||ART_message(D5G2;)S[two-input inverter with keeper]
  23 Ngeneric:Invisible-Pin|pin@6||-4|25|||||ART_message(D5G6;)S[inv2iK]
  24 Ngeneric:Invisible-Pin|pin@7||-4|18|||||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
  25 Ngeneric:Invisible-Pin|pin@8||14.5|-12.5|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
  26 Awire|net@0|||1800|conn@0|y|-8.5|-1|inv2i@0|in[n]|-2.5|-1
  27 Awire|net@1|||1800|conn@1|y|-8.5|1|inv2i@0|in[p]|-2.5|1
  28 Awire|net@2|||1800|inv2i@0|out|2.5|0|pin@3||8|0
  29 Awire|net@3|||2700|pin@3||8|0|invK@0|in|8|3.5
  30 Awire|net@4|||2700|invK@0|out|8|8.5|pin@0||8|10.5
  31 Awire|net@5|||900|pin@1||14.5|10.5|invK@1|in|14.5|8.5
  32 Awire|net@6|||2700|pin@2||14.5|0|invK@1|out|14.5|3.5
  33 Awire|net@7|||1800|pin@0||8|10.5|pin@1||14.5|10.5
  34 Awire|net@8|||1800|pin@3||8|0|pin@2||14.5|0
  35 Awire|net@9|||1800|pin@2||14.5|0|conn@2|a|22|0
  36 Ein[n]||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2;)F0.33
  37 Ein[p]||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
  38 Eout||D5G2;|conn@2|y|O|ATTR_le(D5G1;NY2;)I1
  39 X