chips/marina/electric/purpleFive.delib/inv2iKpD.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LredFive|redFive
   8
   9 # Cell inv2iKpD;1{sch}
  10 Cinv2iKpD;1{sch}||schematic|1021415734000|1159376918981||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
  11 IorangeTSMC090nm:NMOSxwk;1{ic}|NMOSwk@0||4.5|5.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/10.
  12 Ngeneric:Facet-Center|art@0||0|0||||AV
  13 NOff-Page|conn@0||15|0||||
  14 NOff-Page|conn@1||-10.5|1|||Y|
  15 NOff-Page|conn@2||-10.5|-1|||Y|
  16 NOff-Page|conn@3||-4|-6||||
  17 NGround|gnd@0||4.5|11||-1|Y|
  18 IredFive:inv2iCTLp;1{ic}|inv2iCTL@0||0|0|||D0G4;|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X
  19 Iinv2iKpD;1{ic}|inv2iKpD@0||28|12|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
  20 Ngeneric:Invisible-Pin|pin@0||1|14|||||ART_message(D5G2;)S["set input is P, reset input is N"]
  21 NWire_Pin|pin@1||-4.5|5.5||||
  22 NWire_Pin|pin@2||4.5|0||||
  23 Ngeneric:Invisible-Pin|pin@3||21.5|-8|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
  24 Ngeneric:Invisible-Pin|pin@4||0|17|||||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
  25 Ngeneric:Invisible-Pin|pin@5||0|24|||||ART_message(D5G6;)S[inv2iKpD]
  26 Ngeneric:Invisible-Pin|pin@6||0|19|||||ART_message(D5G2;)S[degradable two-input inverter with p-side keeper]
  27 Ngeneric:Invisible-Pin|pin@7||23.5|5.5|||||SIM_spice_card(D6G1;)S[.ic v(out) 'vlo']
  28 NWire_Pin|pin@8||-4.5|1||||
  29 Ngeneric:Invisible-Pin|pin@9||24.5|0|||||VERILOG_code(D6G1;)S[initial begin,    force out = 0;, #30000 release out;,end]
  30 NWire_Pin|pin@10||0|-6||||
  31 Awire|net@0|||2700|pin@2||4.5|0|NMOSwk@0|s|4.5|3.5
  32 Awire|net@1|||2700|NMOSwk@0|d|4.5|7.5|gnd@0||4.5|9.5
  33 Awire|net@2|||1800|pin@1||-4.5|5.5|NMOSwk@0|g|1.5|5.5
  34 Awire|net@3|||1800|pin@8||-4.5|1|inv2iCTL@0|inP|-2.5|1
  35 Awire|net@4|||900|inv2iCTL@0|ctl|0|-2|pin@10||0|-6
  36 Awire|net@5|||1800|inv2iCTL@0|out|2.5|0|pin@2||4.5|0
  37 Awire|net@6|||1800|conn@2|y|-8.5|-1|inv2iCTL@0|inN|-2.5|-1
  38 Awire|net@7|||0|conn@0|a|13|0|pin@2||4.5|0
  39 Awire|net@8|||1800|conn@1|y|-8.5|1|pin@8||-4.5|1
  40 Awire|net@9|||2700|pin@8||-4.5|1|pin@1||-4.5|5.5
  41 Awire|net@10|||0|pin@10||0|-6|conn@3|y|-2|-6
  42 Ectl||D4G2;|conn@3|a|I|ATTR_le(D5G1;NX1;Y-2;)F1.33
  43 Ein[n]||D5G2;|conn@2|a|I|ATTR_le(D5G1;NY2;)F0.33
  44 Ein[p]||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F1.33
  45 Eout||D5G2;|conn@0|y|O|ATTR_le(D5G1;NY2;)D1.67
  46 X