chips/marina/electric/purpleFive.delib/invLT.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell invLT;2{sch}
   8 CinvLT;2{sch}||schematic|1021415734000|1159375615839||ATTR_Delay(D5G1;HNPX-12;Y-5;)I100|ATTR_LEGATE(D5G1;HNPTX-12;Y-10;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-6;)I-1|ATTR_X(D5G1;HNOJPX-12;Y-4;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-12;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-9;)Sstrong1|ATTR_su(D5G1;HNPTX-12;Y-7;)I-1|prototype_center()I[0,0]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-8.5|0||||
  11 NOff-Page|conn@1||8|0||||
  12 IredFive:invLT;1{ic}|invLT@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
  13 IinvLT;1{ic}|invLT@1||16|10.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
  14 Ngeneric:Invisible-Pin|pin@0||18.5|-10.5|||||ART_message(D5G2;)S[X is drive strength,N drive strength is twice P strength]
  15 Ngeneric:Invisible-Pin|pin@1||0.5|17|||||ART_message(D5G2;)S[This is a 2 to 2 width ratio inverter]
  16 Ngeneric:Invisible-Pin|pin@2||0|19|||||ART_message(D5G2;)S[LO-threshold inverter]
  17 Ngeneric:Invisible-Pin|pin@3||-1|24|||||ART_message(D5G6;)S[invLT]
  18 Awire|net@0|||1800|conn@0|y|-6.5|0|invLT@0|in|-2.5|0
  19 Awire|net@1|||0|conn@1|a|6|0|invLT@0|out|2.5|0
  20 Ein||D5G2;|conn@0|a|I|ATTR_le(D5G1;NX-0.5;Y-1.5;)F1.33
  21 Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;NY2;)F1.33
  22 X