migrate jelib->delib
[fleet.git] / chips / marina / electric / purpleFive.delib / inv_passgate.sch
1 HpurpleFive|8.10k
2
3 # External Libraries:
4
5 LorangeTSMC090nm|orangeTSMC090nm
6
7 LredFive|redFive
8
9 # Cell inv_passgate;1{sch}
10 Cinv_passgate;1{sch}||schematic|1021415734000|1159377687524||ATTR_Delay(D5G1;HNPX-12;Y-5.5;)I100|ATTR_LEGATE(D5G1;HNPTX-12;Y-10.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-6.5;)I-1|ATTR_X(D5G1;HNOJPX-12.5;Y-4.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-12;Y-7.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-8.5;)Sstrong1|ATTR_su(D5G1;HNPTX-12;Y-9.5;)I-1|prototype_center()I[0,0]
11 IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||10|0|RRR||D0G4;|ATTR_Delay(D5G1;NPX3.5;)I100|ATTR_X(D5G1.5;NOJPX-0.5;Y2.5;)S@X*2.0
12 Ngeneric:Facet-Center|art@0||0|0||||AV
13 NOff-Page|conn@0||-14|0||||
14 NOff-Page|conn@1||18|0||||
15 NOff-Page|conn@2||4|7||||
16 IredFive:invLT;1{ic}|invLT@0||0.5|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
17 Iinv_passgate;1{ic}|inv_pass@0||20|13.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX-0.5;Y3;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)S""
18 Ngeneric:Invisible-Pin|pin@0||-1.5|20|||||ART_message(D5G6;)S[inv_passgate]
19 Ngeneric:Invisible-Pin|pin@1||-2|14.5|||||ART_message(D5G2;)S[one-parameter inverter]
20 Ngeneric:Invisible-Pin|pin@2||11|-12|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
21 Ngeneric:Invisible-Pin|pin@3||-2|12.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
22 NWire_Pin|pin@4||10|7||||
23 Awire|net@0|||0|NMOS@0|s|8|0|invLT@0|out|3|0
24 Awire|net@1|||0|conn@1|a|16|0|NMOS@0|d|12|0
25 Awire|net@2|||2700|NMOS@0|g|10|3|pin@4||10|7
26 Awire|net@3|||1800|conn@0|y|-12|0|invLT@0|in|-2|0
27 Awire|net@4|||0|pin@4||10|7|conn@2|y|6|7
28 Een||D4G2;|conn@2|a|I|ATTR_le(D5G1;NY-1;)F0.67
29 Ein||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY-2;)F1.33
30 Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;N)D1.33
31 X