chips/marina/electric/purpleFive.delib/nand2_sy.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell nand2_sy;1{sch}
   8 Cnand2_sy;1{sch}||schematic|1021415734000|1159375680290||ATTR_Delay(D5G1;HNPX-16.5;Y-8.5;)I100|ATTR_LEGATE(D5G1;HNPTX-16.5;Y-12.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-16.5;Y-7.5;)I-1|ATTR_X(D5G1;HNOJPX-16.5;Y-6.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-16.5;Y-10.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-16.5;Y-11.5;)Sstrong1|ATTR_su(D5G1;HNPTX-16.5;Y-9.5;)I-1|prototype_center()I[0,0]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-14.5|2.5||||
  11 NOff-Page|conn@1||11.5|0|||Y|
  12 NOff-Page|conn@2||-14.5|-2.5||||
  13 IredFive:nand2_sy;1{ic}|nand2_sy@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2.5;Y-3;)S@Delay|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)S@X|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  14 Inand2_sy;1{ic}|nand2_sy@1||17.5|13|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
  15 NWire_Pin|pin@0||-7.5|-1||||
  16 NWire_Pin|pin@1||-7.5|-2.5||||
  17 NWire_Pin|pin@2||-7.5|1||||
  18 NWire_Pin|pin@3||-7.5|2.5||||
  19 Ngeneric:Invisible-Pin|pin@4||16|-14.5|||||ART_message(D5G2;)S[X is drive strength,One pull-up has the same strength,as the pull-down]
  20 Ngeneric:Invisible-Pin|pin@5||-2|16|||||ART_message(D5G2;)S[P to N width ratio is 1 to 1]
  21 Ngeneric:Invisible-Pin|pin@6||-2|23|||||ART_message(D5G6;)S[nand2_sy]
  22 Ngeneric:Invisible-Pin|pin@7||-2|18|||||ART_message(D5G2;)S[symetric one-parameter NAND]
  23 Awire|net@0|||0|nand2_sy@0|ina|-2.5|-1|pin@0||-7.5|-1
  24 Awire|net@1|||1800|nand2_sy@0|out|2.5|0|conn@1|a|9.5|0
  25 Awire|net@2|||0|nand2_sy@0|inb|-2.5|1|pin@2||-7.5|1
  26 Awire|net@3|||900|pin@0||-7.5|-1|pin@1||-7.5|-2.5
  27 Awire|net@4|||0|pin@1||-7.5|-2.5|conn@2|y|-12.5|-2.5
  28 Awire|net@5|||2700|pin@2||-7.5|1|pin@3||-7.5|2.5
  29 Awire|net@6|||0|pin@3||-7.5|2.5|conn@0|y|-12.5|2.5
  30 Eina||D5G2;|conn@2|a|I|ATTR_le(D5G1;NX0.5;Y2;)F1.33
  31 Einb||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY1.5;)F1.33
  32 Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;NX-0.5;Y-2.5;)I2
  33 X