chips/marina/electric/redFive.delib/inv2i.sch

   1 HredFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 # Cell inv2i;1{sch}
   8 Cinv2i;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-13.25;Y-11.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-13.25;Y-10.25;)S1|ATTR_drive0(D5G1;HNPTX-13.25;Y-12.25;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.25;Y-13.25;)Sstrong1|prototype_center()I[0,0]
   9 IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||0|-5|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  10 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||0|6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||-17.5|-5||||
  13 NOff-Page|conn@1||-17.5|6||||
  14 NOff-Page|conn@2||19|0||||
  15 NGround|gnd@0||0|-12||||
  16 Iinv2i;1{ic}|inv2i@0||25|13|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  17 Ngeneric:Invisible-Pin|pin@0||0.5|22|||||ART_message(D5G6;)S[inv2i]
  18 Ngeneric:Invisible-Pin|pin@1||0|18.5|||||ART_message(D5G2;)S[two-input inverter]
  19 Ngeneric:Invisible-Pin|pin@2||28.5|-6|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
  20 Ngeneric:Invisible-Pin|pin@3||0|16.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
  21 NWire_Pin|pin@4||0|0||||
  22 NPower|pwr@0||0|11.5||||
  23 Awire|net@0|||0|PMOS@0|g|-3|6|conn@1|y|-15.5|6
  24 Awire|net@1|||1800|conn@0|y|-15.5|-5|NMOS@0|g|-3|-5
  25 Awire|net@2|||1800|pin@4||0|0|conn@2|a|17|0
  26 Awire|net@3|||900|pwr@0||0|11.5|PMOS@0|s|0|8
  27 Awire|net@4|||2700|pin@4||0|0|PMOS@0|d|0|4
  28 Awire|net@5|||2700|gnd@0||0|-10|NMOS@0|s|0|-7
  29 Awire|net@6|||900|pin@4||0|0|NMOS@0|d|0|-3
  30 Ein[n]||D5G2;|conn@0|a|I
  31 Ein[p]||D5G2;|conn@1|a|I
  32 Eout||D5G2;|conn@2|y|O
  33 X