chips/marina/electric/redFive.delib/nand2HLT_sy.sch

   1 HredFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 # Cell nand2HLT_sy;1{sch}
   8 Cnand2HLT_sy;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-13.5;Y-16;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-13.5;Y-15;)S1|ATTR_drive0(D5G1;HNPTX-13.5;Y-17;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-18;)Sstrong1|ATTR_verilog_template(D5G1;NTX24.5;Y-20;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
   9 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||6|3.25|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S3.*@X/4.
  10 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@1||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S3.*@X/4.
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||-17|-9.75||||
  13 NOff-Page|conn@1||21|-5.75|||RR|
  14 NOff-Page|conn@2||22.5|0||||
  15 Inand2HLT_sy;1{ic}|nand2HLT@0||38|18.5|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.5;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  16 Inms2_sy;1{ic}|nms2_sy@0||0|-9.75|||D0G4;|ATTR_Delay(D5G1;NOJPX5.5;Y-0.5;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-3.75;Y2.5;)S@X
  17 Ngeneric:Invisible-Pin|pin@18||32|-14|||||ART_message(D5G2;)S[X is drive strength,The pull-down is 1.5 times as strong as,one pull-up; or both pull-ups together,are as strong as the pull-down]
  18 NWire_Pin|pin@19||-9.5|4||||
  19 NWire_Pin|pin@20||-5|0||||
  20 NWire_Pin|pin@21||-9.5|-9.75||||
  21 NWire_Pin|pin@22||6|0||||
  22 NWire_Pin|pin@23||10.25|3.25||||
  23 NWire_Pin|pin@24||10.25|-5.75||||
  24 Ngeneric:Invisible-Pin|pin@25||3.5|25|||||ART_message(D5G6;)S[nand2HLT_sy]
  25 NWire_Pin|pin@26||-5|7.5||||
  26 NWire_Pin|pin@27||6|7.5||||
  27 Ngeneric:Invisible-Pin|pin@28||2|20|||||ART_message(D5G2;)S[high-LO-threshold NAND]
  28 Ngeneric:Invisible-Pin|pin@29||2.5|18|||||ART_message(D5G2;)S[P to N width ratio is 1.5 to 2]
  29 Ngeneric:Invisible-Pin|pin@30||3|16|||||ART_message(D5G2;)S[Sized assuming both inputs go low together]
  30 NWire_Pin|pin@31||0|0||||
  31 NPower|pwr@0||-5|10.5||||
  32 Awire|net@30|||2700|pin@21||-9.5|-9.75|pin@19||-9.5|4
  33 Awire|net@31|||2700|pin@24||10.25|-5.75|pin@23||10.25|3.25
  34 Awire|net@32|||0|pin@27||6|7.5|pin@26||-5|7.5
  35 Awire|net@33|||2700|pin@26||-5|7.5|pwr@0||-5|10.5
  36 Awire|net@34|||2700|pin@22||6|0|PMOS@0|d|6|1.25
  37 Awire|net@35|||1800|PMOS@0|g|9|3.25|pin@23||10.25|3.25
  38 Awire|net@36|||2700|PMOS@0|s|6|5.25|pin@27||6|7.5
  39 Awire|net@37|||2700|pin@20||-5|0|PMOS@1|d|-5|2
  40 Awire|net@38|||1800|pin@19||-9.5|4|PMOS@1|g|-8|4
  41 Awire|net@39|||900|pin@26||-5|7.5|PMOS@1|s|-5|6
  42 Awire|net@40|||0|pin@31||0|0|pin@20||-5|0
  43 Awire|net@41|||0|pin@22||6|0|pin@31||0|0
  44 Awire|net@42|||900|pin@31||0|0|nms2_sy@0|d|0|-3.75
  45 Awire|net@43|||0|pin@24||10.25|-5.75|nms2_sy@0|g2|3|-5.75
  46 Awire|net@44|||0|nms2_sy@0|g|-3|-9.75|pin@21||-9.5|-9.75
  47 Awire|net@45|||0|conn@2|a|20.5|0|pin@22||6|0
  48 Awire|net@46|||0|conn@1|y|19|-5.75|pin@24||10.25|-5.75
  49 Awire|net@47|||0|pin@21||-9.5|-9.75|conn@0|y|-15|-9.75
  50 Eina||D5G2;|conn@0|a|I
  51 Einb||D5G2;|conn@1|a|I
  52 Eout||D5G2;|conn@2|y|O
  53 X