chips/marina/electric/redFive.delib/nand3LT_sy3.sch

   1 HredFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 # Cell nand3LT_sy3;1{sch}
   8 Cnand3LT_sy3;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-30;Y-12.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-30;Y-11.5;)S1|ATTR_drive0(D5G1;HNPTX-30;Y-13.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-30;Y-14.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX19;Y-24;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb), $(inc));|prototype_center()I[0,0]
   9 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||-14|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/3.
  10 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@1||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/3.
  11 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@2||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/3.
  12 Ngeneric:Facet-Center|art@0||0|0||||AV
  13 NOff-Page|conn@0||-34.5|-2.5||||
  14 NOff-Page|conn@1||24|-12.5|||RR|
  15 NOff-Page|conn@2||27|0||||
  16 NOff-Page|conn@3||-35|4||||
  17 Inand3LT_sy3;1{ic}|nand3LT_@0||35|19.5|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_LEGATE()I1|ATTR_su()I-1
  18 Inms3_sy3;1{ic}|nms3_sy3@0||-10|-16.5|||D0G4;|ATTR_Delay(D5G1;NOJPX-8.5;Y-1.5;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-8.5;Y1;)S@X
  19 NWire_Pin|pin@10||-19.5|-8.5||||
  20 NWire_Pin|pin@11||-21.5|-16.5||||
  21 NWire_Pin|pin@12||10.5|-12.5||||
  22 NWire_Pin|pin@13||-19.5|4||||
  23 NWire_Pin|pin@14||-21.5|-2.5||||
  24 NWire_Pin|pin@15||-9|-2.5||||
  25 NWire_Pin|pin@16||-5|7.5||||
  26 NWire_Pin|pin@17||4.5|7.5||||
  27 NWire_Pin|pin@18||-14|7.5||||
  28 Ngeneric:Invisible-Pin|pin@19||0|16.5|||||ART_message(D5G2;)S[Sized assuming that all 3 inputs go low together]
  29 Ngeneric:Invisible-Pin|pin@20||28.5|-19|||||ART_message(D5G2;)S[X is drive strength,Three pull-ups have the same strength,as the pull-down]
  30 Ngeneric:Invisible-Pin|pin@21||-0.5|18|||||ART_message(D5G2;)S[P to N width ratio is 2/3 to 3]
  31 NWire_Pin|pin@22||-9|4||||
  32 NWire_Pin|pin@23||-5|0||||
  33 Ngeneric:Invisible-Pin|pin@24||-0.5|20|||||ART_message(D5G2;)S[one-parameter NAND]
  34 NWire_Pin|pin@25||4.5|0||||
  35 NWire_Pin|pin@26||10.5|4||||
  36 Ngeneric:Invisible-Pin|pin@27||-0.5|25|||||ART_message(D5G6;)S[nand3LT_sy3]
  37 NWire_Pin|pin@28||-14|0||||
  38 NPower|pwr@0||-5|10.5||||
  39 Awire|net@16|||1800|pin@23||-5|0|pin@25||4.5|0
  40 Awire|net@25|||1800|pin@10||-19.5|-8.5|nms3_sy3@0|g3|-13|-8.5
  41 Awire|net@26|||900|pin@13||-19.5|4|pin@10||-19.5|-8.5
  42 Awire|net@27|||1800|pin@11||-21.5|-16.5|nms3_sy3@0|g|-13|-16.5
  43 Awire|net@28|||900|pin@14||-21.5|-2.5|pin@11||-21.5|-16.5
  44 Awire|net@29|||0|pin@12||10.5|-12.5|nms3_sy3@0|g2|1.5|-12.5
  45 Awire|net@30|||2700|pin@12||10.5|-12.5|pin@26||10.5|4
  46 Awire|net@31|||900|pin@23||-5|0|nms3_sy3@0|d|-5|-5.5
  47 Awire|net@32|||900|pin@18||-14|7.5|PMOS@0|s|-14|6
  48 Awire|net@33|||1800|pin@13||-19.5|4|PMOS@0|g|-17|4
  49 Awire|net@34|||2700|pin@28||-14|0|PMOS@0|d|-14|2
  50 Awire|net@35|||900|pin@16||-5|7.5|PMOS@1|s|-5|6
  51 Awire|net@36|||1800|pin@22||-9|4|PMOS@1|g|-8|4
  52 Awire|net@37|||2700|pin@23||-5|0|PMOS@1|d|-5|2
  53 Awire|net@38|||2700|PMOS@2|s|4.5|6|pin@17||4.5|7.5
  54 Awire|net@39|||0|pin@26||10.5|4|PMOS@2|g|7.5|4
  55 Awire|net@40|||2700|pin@25||4.5|0|PMOS@2|d|4.5|2
  56 Awire|net@41|||0|pin@15||-9|-2.5|pin@14||-21.5|-2.5
  57 Awire|net@42|||2700|pin@15||-9|-2.5|pin@22||-9|4
  58 Awire|net@43|||2700|pin@16||-5|7.5|pwr@0||-5|10.5
  59 Awire|net@44|||0|pin@17||4.5|7.5|pin@16||-5|7.5
  60 Awire|net@45|||0|pin@16||-5|7.5|pin@18||-14|7.5
  61 Awire|net@46|||0|pin@23||-5|0|pin@28||-14|0
  62 Awire|net@47|||0|conn@2|a|25|0|pin@25||4.5|0
  63 Awire|net@48|||0|conn@1|y|22|-12.5|pin@12||10.5|-12.5
  64 Awire|net@49|||0|pin@13||-19.5|4|conn@3|y|-33|4
  65 Awire|net@50|||1800|conn@0|y|-32.5|-2.5|pin@14||-21.5|-2.5
  66 Eina||D5G2;|conn@0|a|I
  67 Einb||D5G2;|conn@1|a|I
  68 Einc||D5G2;|conn@3|y|I
  69 Eout||D5G2;|conn@2|y|O
  70 X