chips/marina/electric/redFive.delib/nand3LTen.sch

   1 HredFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 # Cell nand3LTen;1{sch}
   8 Cnand3LTen;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-30;Y-12.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-30;Y-11.5;)S1|ATTR_drive0(D5G1;HNPTX-30;Y-13.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-30;Y-14.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX19;Y-23;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb), $(inc));|prototype_center()I[0,0]
   9 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX1.5;Y2.5;)Smax(@X/20., 5./6.)
  10 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@1||-14|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/2.
  11 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@2||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/2.
  12 Ngeneric:Facet-Center|art@0||0|0||||AV
  13 NOff-Page|conn@0||-27.5|-2.5||||
  14 NOff-Page|conn@1||17|4|||RR|
  15 NOff-Page|conn@2||0|11|||R|
  16 NOff-Page|conn@3||-28|4||||
  17 Inand3LTen;1{ic}|nand3LTe@0||44|9|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_LEGATE()I1|ATTR_su()I-1
  18 Inms3;1{ic}|nms3@0||-5|-16.5|||D0G4;|ATTR_Delay(D5G1;NOJPX3;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-2;Y0.5;)S@X
  19 Ngeneric:Invisible-Pin|pin@0||0|20.5|||||ART_message(D5G2;)S["three input, fixed-size low-threshold NAND where ina is DC signal (enable)"]
  20 NWire_Pin|pin@1||-19.5|-8.5||||
  21 NWire_Pin|pin@2||-21.5|-16.5||||
  22 NWire_Pin|pin@3||10.5|-12.5||||
  23 NWire_Pin|pin@4||-19.5|4||||
  24 NWire_Pin|pin@5||-21.5|-2.5||||
  25 NWire_Pin|pin@6||-9|-2.5||||
  26 NWire_Pin|pin@7||-5|7.5||||
  27 NWire_Pin|pin@8||4.5|7.5||||
  28 NWire_Pin|pin@9||-14|7.5||||
  29 Ngeneric:Invisible-Pin|pin@10||-1|15.5|||||ART_message(D5G2;)S[Sized assuming that all 3 inputs go low together (but one p/u is weak)]
  30 Ngeneric:Invisible-Pin|pin@11||28.5|-16|||||ART_message(D5G2;)S[X is drive strength,Two pull-ups have the same strength,as the pull-down]
  31 Ngeneric:Invisible-Pin|pin@12||-0.5|18|||||ART_message(D5G2;)S[P to N width ratio is 1 to 3]
  32 NWire_Pin|pin@13||-9|4||||
  33 NWire_Pin|pin@14||0|0||||
  34 NWire_Pin|pin@15||-5|0||||
  35 NWire_Pin|pin@16||4.5|0||||
  36 NWire_Pin|pin@17||10.5|4||||
  37 Ngeneric:Invisible-Pin|pin@18||-0.5|25|||||ART_message(D5G6;)S[nand3LTen]
  38 NWire_Pin|pin@19||-14|0||||
  39 NPower|pwr@0||-5|10.5||||
  40 Awire|net@0|||900|pin@7||-5|7.5|PMOS@0|s|-5|6
  41 Awire|net@1|||1800|pin@13||-9|4|PMOS@0|g|-8|4
  42 Awire|net@2|||2700|pin@15||-5|0|PMOS@0|d|-5|2
  43 Awire|net@3|||900|pin@15||-5|0|nms3@0|d|-5|-6.5
  44 Awire|net@4|||900|pin@4||-19.5|4|pin@1||-19.5|-8.5
  45 Awire|net@5|||900|pin@5||-21.5|-2.5|pin@2||-21.5|-16.5
  46 Awire|net@6|||2700|pin@3||10.5|-12.5|pin@17||10.5|4
  47 Awire|net@7|||900|pin@9||-14|7.5|PMOS@1|s|-14|6
  48 Awire|net@8|||1800|pin@4||-19.5|4|PMOS@1|g|-17|4
  49 Awire|net@9|||2700|pin@19||-14|0|PMOS@1|d|-14|2
  50 Awire|net@10|||2700|PMOS@2|s|4.5|6|pin@8||4.5|7.5
  51 Awire|net@11|||0|pin@17||10.5|4|PMOS@2|g|7.5|4
  52 Awire|net@12|||2700|pin@16||4.5|0|PMOS@2|d|4.5|2
  53 Awire|net@13|||1800|conn@3|y|-26|4|pin@4||-19.5|4
  54 Awire|net@14|||0|pin@6||-9|-2.5|pin@5||-21.5|-2.5
  55 Awire|net@15|||0|pin@5||-21.5|-2.5|conn@0|y|-25.5|-2.5
  56 Awire|net@16|||2700|pin@6||-9|-2.5|pin@13||-9|4
  57 Awire|net@17|||2700|pin@7||-5|7.5|pwr@0||-5|10.5
  58 Awire|net@18|||0|pin@8||4.5|7.5|pin@7||-5|7.5
  59 Awire|net@19|||0|pin@7||-5|7.5|pin@9||-14|7.5
  60 Awire|net@20|||2700|pin@14||0|0|conn@2|a|0|9
  61 Awire|net@21|||0|pin@16||4.5|0|pin@14||0|0
  62 Awire|net@22|||0|pin@14||0|0|pin@15||-5|0
  63 Awire|net@23|||1800|pin@17||10.5|4|conn@1|y|15|4
  64 Awire|net@24|||0|pin@15||-5|0|pin@19||-14|0
  65 Awire|net@25|||1800|pin@2||-21.5|-16.5|nms3@0|g|-8|-16.5
  66 Awire|net@26|||0|pin@3||10.5|-12.5|nms3@0|g2|-2|-12.5
  67 Awire|net@27|||1800|pin@1||-19.5|-8.5|nms3@0|g3|-8|-8.5
  68 Eina||D5G2;|conn@0|a|I
  69 Einb||D5G2;|conn@1|a|I
  70 Einc||D5G2;|conn@3|y|I
  71 Eout||D5G2;|conn@2|y|O
  72 X