chips/marina/electric/redFive.delib/nand3MLT.sch

   1 HredFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 # Cell nand3MLT;1{sch}
   8 Cnand3MLT;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-29;Y-7;)I100|ATTR_X(D5G1;HNOLPX-29;Y-6;)S1|ATTR_drive0(D5G1;HNPTX-29;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-29;Y-9;)Sstrong1|ATTR_verilog_template(D5G1;NTX20.5;Y-17.5;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb), $(inc));|prototype_center()I[0,0]
   9 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/2.
  10 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@1||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/2.
  11 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@2||-14|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X/2.
  12 Ngeneric:Facet-Center|art@0||0|0||||AV
  13 NOff-Page|conn@0||-34.5|4||||
  14 NOff-Page|conn@1||28.5|10||||
  15 NOff-Page|conn@2||23|-1|||RR|
  16 NOff-Page|conn@3||-23|-12||||
  17 Inand3MLT;1{ic}|nand3MLT@0||38|26|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  18 Inms3;1{ic}|nms3@0||0|-12|||D0G4;|ATTR_Delay(D5G1;NOJPX3;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-2;Y0.5;)S@X
  19 NWire_Pin|pin@15||0|10||||
  20 Ngeneric:Invisible-Pin|pin@26||33|-10.5|||||ART_message(D5G2;)S[X is drive strength,Two pull-ups have the same strength,as the pull-down]
  21 Ngeneric:Invisible-Pin|pin@27||0|21|||||ART_message(D5G2;)S[Sized assuming at least 2 of 3 inputs go low together]
  22 Ngeneric:Invisible-Pin|pin@28||-0.5|23|||||ART_message(D5G2;)S[P to N width ratio is 1 to 3]
  23 NWire_Pin|pin@29||9|-8||||
  24 NWire_Pin|pin@30||-18|-4||||
  25 NWire_Pin|pin@31||-18|4||||
  26 NWire_Pin|pin@32||-14|0||||
  27 Ngeneric:Invisible-Pin|pin@33||-0.5|30|||||ART_message(D5G6;)S[nand3MLT]
  28 NWire_Pin|pin@34||9|4||||
  29 NWire_Pin|pin@35||4.5|0||||
  30 Ngeneric:Invisible-Pin|pin@36||-0.5|25|||||ART_message(D5G2;)S["three input, fixed-size NAND"]
  31 NWire_Pin|pin@37||-5|0||||
  32 NWire_Pin|pin@38||0|0||||
  33 NWire_Pin|pin@39||-9|4||||
  34 NWire_Pin|pin@40||-9|-12||||
  35 NWire_Pin|pin@41||4.5|7.5||||
  36 NWire_Pin|pin@42||-14|7.5||||
  37 NWire_Pin|pin@43||-5|7.5||||
  38 NWire_Pin|pin@44||9|-1||||
  39 NPower|pwr@0||-5|11.5||||
  40 Awire|net@30|||2700|pin@40||-9|-12|pin@39||-9|4
  41 Awire|net@33|||2700|pin@38||0|0|pin@15||0|10
  42 Awire|net@42|||0|pin@29||9|-8|nms3@0|g2|3|-8
  43 Awire|net@43|||0|nms3@0|g3|-3|-4|pin@30||-18|-4
  44 Awire|net@44|||2700|pin@30||-18|-4|pin@31||-18|4
  45 Awire|net@45|||0|pin@37||-5|0|pin@32||-14|0
  46 Awire|net@46|||0|nms3@0|g|-3|-12|pin@40||-9|-12
  47 Awire|net@47|||900|pin@38||0|0|nms3@0|d|0|-2
  48 Awire|net@48|||0|pin@38||0|0|pin@37||-5|0
  49 Awire|net@49|||0|pin@35||4.5|0|pin@38||0|0
  50 Awire|net@50|||2700|pin@37||-5|0|PMOS@0|d|-5|2
  51 Awire|net@51|||1800|pin@39||-9|4|PMOS@0|g|-8|4
  52 Awire|net@52|||2700|pin@35||4.5|0|PMOS@1|d|4.5|2
  53 Awire|net@53|||1800|PMOS@1|g|7.5|4|pin@34||9|4
  54 Awire|net@54|||2700|pin@32||-14|0|PMOS@2|d|-14|2
  55 Awire|net@55|||0|PMOS@2|g|-17|4|pin@31||-18|4
  56 Awire|net@56|||900|pin@41||4.5|7.5|PMOS@1|s|4.5|6
  57 Awire|net@57|||2700|PMOS@2|s|-14|6|pin@42||-14|7.5
  58 Awire|net@58|||1800|pin@43||-5|7.5|pin@41||4.5|7.5
  59 Awire|net@59|||1800|pin@42||-14|7.5|pin@43||-5|7.5
  60 Awire|net@60|||900|pin@43||-5|7.5|PMOS@0|s|-5|6
  61 Awire|net@61|||2700|pin@43||-5|7.5|pwr@0||-5|11.5
  62 Awire|net@62|||900|pin@44||9|-1|pin@29||9|-8
  63 Awire|net@63|||900|pin@34||9|4|pin@44||9|-1
  64 Awire|net@64|||0|conn@2|y|21|-1|pin@44||9|-1
  65 Awire|net@65|||0|conn@1|a|26.5|10|pin@15||0|10
  66 Awire|net@70|||1800|conn@3|y|-21|-12|pin@40||-9|-12
  67 Awire|net@71|||1800|conn@0|y|-32.5|4|pin@31||-18|4
  68 Eina||D5G2;|conn@3|a|I
  69 Einb||D5G2;|conn@2|a|I
  70 Einc||D5G2;|conn@0|y|I
  71 Eout||D5G2;|conn@1|y|O
  72 X