chips/marina/electric/redFive.delib/nand3en_sy.sch

   1 HredFive|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 # Cell nand3en_sy;1{sch}
   8 Cnand3en_sy;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-29;Y-7;)I100|ATTR_X(D5G1;HNOLPX-29;Y-6;)S1|ATTR_drive0(D5G1;HNPTX-29;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-29;Y-9;)Sstrong1|ATTR_verilog_template(D5G1;NTX20.5;Y-17.5;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb), $(inc));|prototype_center()I[0,0]
   9 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX2;Y2.5;)Smax(@X/10., 5./6.)
  10 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@1||-14|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  11 IorangeTSMC090nm:PMOSx;1{ic}|PMOS@2||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
  12 Ngeneric:Facet-Center|art@0||0|0||||AV
  13 NOff-Page|conn@0||-15|-13||||
  14 NOff-Page|conn@1||14|-1|||RR|
  15 NOff-Page|conn@2||0|14.5|||R|
  16 NOff-Page|conn@3||-22|4||||
  17 Inand3en_sy;1{ic}|nand3en_@0||29|14|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  18 Inms3_2sy;1{ic}|nms3_2sy@0||0|-13|||D0G4;|ATTR_Delay(D5G1;NOJPX5;Y-1.5;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-3.75;Y2.5;)S@X
  19 Inms3_2sy;1{ic}|nms3_2sy@1||0|-13|||D0G4;|ATTR_Delay(D5G1;NOJPX5;Y-1.5;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-3.75;Y2.5;)S@X
  20 NWire_Pin|pin@0||-18|-5||||
  21 NWire_Pin|pin@1||-5|7.5||||
  22 NWire_Pin|pin@2||-14|7.5||||
  23 NWire_Pin|pin@3||4.5|7.5||||
  24 Ngeneric:Invisible-Pin|pin@4||30|-10|||||ART_message(D5G2;)S[X is drive strength,Each pull-up has the same strength,as the pull-down]
  25 Ngeneric:Invisible-Pin|pin@5||-0.5|19.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 3]
  26 NWire_Pin|pin@6||-9|4||||
  27 NWire_Pin|pin@7||0|0||||
  28 NWire_Pin|pin@8||-5|0||||
  29 Ngeneric:Invisible-Pin|pin@9||-0.5|22|||||ART_message(D5G2;)S["three input, fixed-size NAND where ina is DC signal (enable) and inb/c are symmetric"]
  30 NWire_Pin|pin@10||-9|-13||||
  31 NWire_Pin|pin@11||4.5|0||||
  32 NWire_Pin|pin@12||9|4||||
  33 NWire_Pin|pin@13||9|-1||||
  34 Ngeneric:Invisible-Pin|pin@14||-0.5|27|||||ART_message(D5G6;)S[nand3en_sy]
  35 NWire_Pin|pin@15||-14|0||||
  36 NWire_Pin|pin@16||-18|4||||
  37 NWire_Pin|pin@17||9|-9||||
  38 NPower|pwr@0||-5|11.5||||
  39 Awire|net@0|||900|pin@1||-5|7.5|PMOS@0|s|-5|6
  40 Awire|net@1|||1800|pin@6||-9|4|PMOS@0|g|-8|4
  41 Awire|net@2|||2700|pin@8||-5|0|PMOS@0|d|-5|2
  42 Awire|net@3|||900|pin@16||-18|4|pin@0||-18|-5
  43 Awire|net@4|||2700|pin@17||9|-9|pin@13||9|-1
  44 Awire|net@5|||1800|pin@10||-9|-13|nms3_2sy@0|g|-2.25|-13
  45 Awire|net@6|||1800|nms3_2sy@0|g2|3|-9|pin@17||9|-9
  46 Awire|net@8|||900|pin@7||0|0|nms3_2sy@0|d|0|-3
  47 Awire|net@9|||2700|pin@1||-5|7.5|pwr@0||-5|11.5
  48 Awire|net@10|||1800|pin@2||-14|7.5|pin@1||-5|7.5
  49 Awire|net@11|||1800|pin@1||-5|7.5|pin@3||4.5|7.5
  50 Awire|net@12|||2700|PMOS@1|s|-14|6|pin@2||-14|7.5
  51 Awire|net@13|||900|pin@3||4.5|7.5|PMOS@2|s|4.5|6
  52 Awire|net@14|||0|PMOS@1|g|-17|4|pin@16||-18|4
  53 Awire|net@15|||2700|pin@15||-14|0|PMOS@1|d|-14|2
  54 Awire|net@16|||1800|PMOS@2|g|7.5|4|pin@12||9|4
  55 Awire|net@17|||2700|pin@11||4.5|0|PMOS@2|d|4.5|2
  56 Awire|net@18|||2700|pin@10||-9|-13|pin@6||-9|4
  57 Awire|net@19|||2700|pin@7||0|0|conn@2|a|0|12.5
  58 Awire|net@20|||0|pin@11||4.5|0|pin@7||0|0
  59 Awire|net@21|||0|pin@7||0|0|pin@8||-5|0
  60 Awire|net@22|||0|pin@10||-9|-13|conn@0|y|-13|-13
  61 Awire|net@23|||2700|pin@13||9|-1|pin@12||9|4
  62 Awire|net@24|||1800|pin@13||9|-1|conn@1|y|12|-1
  63 Awire|net@25|||0|pin@8||-5|0|pin@15||-14|0
  64 Awire|net@26|||0|pin@16||-18|4|conn@3|y|-20|4
  65 Awire|net@27|||0|nms3_2sy@1|g3|-3|-5|pin@0||-18|-5
  66 Eina||D5G2;|conn@0|a|I
  67 Einb||D5G2;|conn@1|a|I
  68 Einc||D5G2;|conn@3|y|I
  69 Eout||D5G2;|conn@2|y|O
  70 X