migrate jelib->delib
[fleet.git] / chips / marina / electric / registersM.delib / aTryA.lay
1 HregistersM|8.10k
2
3 # Cell aTryA;1{lay}
4 CaTryA;1{lay}||cmos90|1230500155786|1238334870912|I
5 Iaddr1in60Cx7;2{lay}|addr1in6@0||1008|144|||D5G4;
6 Iaddr1in60Cx7;2{lay}|addr1in6@1||-1008|144|X||D5G4;
7 Ngeneric:Facet-Center|art@0||0|0||||AV
8 Idata1in60Cx18;3{lay}|data1in6@0||864|-72|||D5G4;
9 Idata1in60Cx18;3{lay}|data1in6@1||-864|-72|X||D5G4;
10 Ametal-2|net@5||1.2|S1800|addr1in6@1|fire|-504|75.9|addr1in6@0|fire|504|75.9
11 Ametal-2|net@6||1.2|S1800|data1in6@1|dcl|-216|-83.7|data1in6@0|dcl|216|-83.7
12 X