chips/marina/electric/registersM.delib/addr1in20Bx15.sch

   1 HregistersM|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 LorangeTSMC090nm|orangeTSMC090nm
   8
   9 # Cell addr1in20Bx15;1{sch}
  10 Caddr1in20Bx15;1{sch}||schematic|1230593509808|1238334870912|I
  11 Iaddr1in20Bx15;1{ic}|addr1in2@0||25.5|17|||D5G4;
  12 Iaddr1in20Bx7;1{ic}|addr1in2@1||-24|0|||D5G4;
  13 Iaddr1in20Bx7;1{ic}|addr1in2@2||24|0|||D5G4;
  14 Ngeneric:Facet-Center|art@0||0|0||||AV
  15 NOff-Page|conn@0||-2|-13|||R|
  16 NOff-Page|conn@1||-33|-7.5||||
  17 NOff-Page|conn@2||29.5|-7.5||||
  18 IlatchesK:latch1in20B;1{ic}|latch1in@1||0|0|||D5G4;
  19 Ngeneric:Invisible-Pin|pin@0||2|43|||||ART_message(D5G6;)Saddr1in20Bx15
  20 Ngeneric:Invisible-Pin|pin@1||1|34|||||ART_message(D5G3;)Sies 21 February 2009
  21 Ngeneric:Invisible-Pin|pin@2||0|38|||||ART_message(D5G4;)Sa complete data register
  22 NBus_Pin|pin@5||31|0|-1|-1||
  23 NBus_Pin|pin@6||31|5.5|-1|-1||
  24 NBus_Pin|pin@8||-17|5|-1|-1||
  25 NBus_Pin|pin@9||-17|0|-1|-1||
  26 NBus_Pin|pin@10||-32|0|-1|-1||
  27 NBus_Pin|pin@12||16|0|-1|-1||
  28 NBus_Pin|pin@13||16|4.5|-1|-1||
  29 NBus_Pin|pin@15||-32|4.5|-1|-1||
  30 NWire_Pin|pin@16||-8|0||||
  31 NWire_Pin|pin@17||-8|4.5||||
  32 NWire_Pin|pin@18||8|0||||
  33 NWire_Pin|pin@19||8|4.5||||
  34 NWire_Pin|pin@20||-26|-7.5||||
  35 NWire_Pin|pin@21||22|-7.5||||
  36 NWire_Pin|pin@23||-2|-7.5||||
  37 IorangeTSMC090nm:wire90;1{ic}|wire90@0||11|-7.5|X||D0G4;|ATTR_L(D5G1;PUD)S2330|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  38 IorangeTSMC090nm:wire90;1{ic}|wire90@1||-12.5|-7.5|X||D0G4;|ATTR_L(D5G1;PUD)S2330|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  39 Abus|ain[1:7]|D5G2;|-0.5|IJ2700|pin@12||16|0|pin@13||16|4.5
  40 Abus|ain[8:14]|D5G2;|-0.5|IJ900|pin@15||-32|4.5|pin@10||-32|0
  41 Awire|ain[TT]|D5G2;||2700|pin@16||-8|0|pin@17||-8|4.5
  42 Abus|aout[1:7]|D5G2;|-0.5|IJ2700|pin@5||31|0|pin@6||31|5.5
  43 Abus|aout[8:14]|D5G2;|-0.5|IJ2700|pin@9||-17|0|pin@8||-17|5
  44 Awire|aout[TT]|D5G2;||2700|pin@18||8|0|pin@19||8|4.5
  45 Abus|net@2||-0.5|IJ1800|addr1in2@2|aout[1:7]|27|0|pin@5||31|0
  46 Abus|net@5||-0.5|IJ0|pin@9||-17|0|addr1in2@1|aout[1:7]|-21|0
  47 Abus|net@6||-0.5|IJ0|addr1in2@1|ain[1:7]|-27|0|pin@10||-32|0
  48 Abus|net@8||-0.5|IJ0|addr1in2@2|ain[1:7]|21|0|pin@12||16|0
  49 Awire|net@13|||0|latch1in@1|in[1]|-3|0|pin@16||-8|0
  50 Awire|net@15|||1800|latch1in@1|out[1]|3|0|pin@18||8|0
  51 Awire|net@17|||900|addr1in2@1|fire|-26|-3|pin@20||-26|-7.5
  52 Awire|net@19|||2700|pin@21||22|-7.5|addr1in2@2|fire|22|-3
  53 Awire|net@23|||900|latch1in@1|hcl|-2|-3|pin@23||-2|-7.5
  54 Awire|net@24|||1800|pin@20||-26|-7.5|wire90@1|b|-15|-7.5
  55 Awire|net@25|||900|pin@23||-2|-7.5|conn@0|y|-2|-11
  56 Awire|net@26|||1800|wire90@1|a|-10|-7.5|pin@23||-2|-7.5
  57 Awire|net@27|||1800|pin@23||-2|-7.5|wire90@0|b|8.5|-7.5
  58 Awire|net@28|||1800|wire90@0|a|13.5|-7.5|pin@21||22|-7.5
  59 Eain[TT,1:14]||D4G2;|conn@1|a|I
  60 Eaout[TT,1:14]||D6G2;|conn@2|y|O
  61 Efire||D4G2;|conn@0|a|I
  62 X