chips/marina/electric/registersM.delib/addr1in60Cx7.sch

   1 HregistersM|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell addr1in60Cx7;1{sch}
   8 Caddr1in60Cx7;1{sch}||schematic|1188688057760|1235218549189|I
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-10|0||||
  11 NOff-Page|conn@1||10|0||||
  12 NOff-Page|conn@2||-2|-9|||R|
  13 Iaddr1in60Cx7;1{ic}|hi1inAdd@0||17|11|||D5G4;
  14 IlatchesK:latch1in60C;1{ic}|lat[1:7]|D5G3;Y4;|0|0|||D5G4;
  15 Ngeneric:Invisible-Pin|pin@0||1.5|29|||||ART_message(D5G6;)Saddr1in60Cx7
  16 Ngeneric:Invisible-Pin|pin@1||0.5|20|||||ART_message(D5G3;)Sies 29 December 2008
  17 Ngeneric:Invisible-Pin|pin@2||-0.5|24|||||ART_message(D5G4;)SHI control address register
  18 Ngeneric:Invisible-Pin|pin@5||-29.5|13|||||ART_message(D6G3;)S[Bit arrangement:,01 02 03 04 05 06 07]
  19 Abus|net@2||-0.5|IJ1800|conn@0|y|-8|0|lat[1:7]|in[1]|-3|0
  20 Abus|net@3||-0.5|IJ1800|lat[1:7]|out[1]|3|0|conn@1|a|8|0
  21 Awire|net@6|||2700|conn@2|y|-2|-7|lat[1:7]|hcl|-2|-3
  22 Eain[1:14]|ain[1:7]|D4G2;|conn@0|a|I
  23 Eaout[1:14]|aout[1:7]|D6G2;|conn@1|y|O
  24 Efire||D4G2;|conn@2|a|I
  25 X