chips/marina/electric/registersM.delib/data1in60Cx18.sch

   1 HregistersM|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell data1in60Cx18;1{sch}
   8 Cdata1in60Cx18;1{sch}||schematic|1188688057760|1230498884248|I
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-10|0||||
  11 NOff-Page|conn@1||10|0||||
  12 NOff-Page|conn@2||-2|-9|||R|
  13 Idata1in60Cx18;1{ic}|hi1inAdd@0||20|8|||D5G4;
  14 IlatchesK:latch1in60C;1{ic}|lat[1:18]|D5G3;Y4;|0|0|||D5G4;
  15 Ngeneric:Invisible-Pin|pin@0||1.5|35|||||ART_message(D5G6;)Sdata1in60Cx18
  16 Ngeneric:Invisible-Pin|pin@1||0.5|26|||||ART_message(D5G3;)Sies 28 December 2008
  17 Ngeneric:Invisible-Pin|pin@2||-0.5|30|||||ART_message(D5G4;)SHI control data register
  18 Ngeneric:Invisible-Pin|pin@3||-4.5|17|||||ART_message(D6G2;)S[Bit arrangement right:,18 17 16 15 14 13 12 11 10,01 02 03 04 05 06 07 08 09]
  19 Ngeneric:Invisible-Pin|pin@4||-7.5|17|||||ART_message(D4G2;)S[Bit arrangement left:,10 11 12 13 14 15 16 17 18,09 08 07 06 05 04 03 02 01]
  20 Abus|net@2||-0.5|IJ1800|conn@0|y|-8|0|lat[1:18]|in[1]|-3|0
  21 Abus|net@3||-0.5|IJ1800|lat[1:18]|out[1]|3|0|conn@1|a|8|0
  22 Awire|net@6|||2700|conn@2|y|-2|-7|lat[1:18]|hcl|-2|-3
  23 Edcl||D4G2;|conn@2|a|I
  24 EinA[1:18]|in[1:18]|D4G2;|conn@0|a|I
  25 Eout[1:18]||D6G2;|conn@1|y|O
  26 X