chips/marina/electric/registersM.delib/data2in60Cx37.sch

   1 HregistersM|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 LorangeTSMC090nm|orangeTSMC090nm
   8
   9 # Cell data2in60Cx37;1{sch}
  10 Cdata2in60Cx37;1{sch}||schematic|1189373179324|1238334870912|I
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@0||32|-6||||
  13 NOff-Page|conn@1||-32|-9||||
  14 NOff-Page|conn@2||-2|-15.5|||YRRR|
  15 NOff-Page|conn@3||-32|9|||XRR|
  16 Idata2in60Cx37;1{ic}|data2in6@0||24|15|||D5G4;
  17 Idata2in60Cx18;1{ic}|data2in6@1||24|0|||D5G4;
  18 Idata2in60Cx18;1{ic}|data2in6@2||-24|0|||D5G4;
  19 IlatchesK:latch2in60C;1{ic}|latch2in@4||0|0|||D5G4;
  20 Ngeneric:Invisible-Pin|pin@0||1|38|||||ART_message(D5G6;)Sdata2in60Cx37
  21 Ngeneric:Invisible-Pin|pin@1||0|29|||||ART_message(D5G3;)Sies 29 December 2008
  22 Ngeneric:Invisible-Pin|pin@2||-1|33|||||ART_message(D5G4;)Sa complete data register
  23 NBus_Pin|pin@18||16|-1|-1|-1||
  24 NBus_Pin|pin@19||16|-5|-1|-1||
  25 NBus_Pin|pin@24||16|1|-1|-1||
  26 NBus_Pin|pin@25||16|5|-1|-1||
  27 NWire_Pin|pin@33||-7|1||||
  28 NWire_Pin|pin@34||-7|4||||
  29 NWire_Pin|pin@35||-7|-1||||
  30 NWire_Pin|pin@36||-7|-4||||
  31 NBus_Pin|pin@39||31|0|-1|-1||
  32 NBus_Pin|pin@40||31|-3|-1|-1||
  33 NWire_Pin|pin@41||7|0||||
  34 NWire_Pin|pin@42||7|-3||||
  35 NBus_Pin|pin@43||-26|-9|-1|-1||
  36 NBus_Pin|pin@44||-2|-9|-1|-1||
  37 NBus_Pin|pin@45||22|-9|-1|-1||
  38 NWire_Pin|pin@47||-2|6||||
  39 NWire_Pin|pin@48||-2|-6||||
  40 NBus_Pin|pin@49||-32|-1|-1|-1||
  41 NBus_Pin|pin@50||-32|-5|-1|-1||
  42 NBus_Pin|pin@51||-32|1|-1|-1||
  43 NBus_Pin|pin@52||-32|5|-1|-1||
  44 NBus_Pin|pin@53||-16|0|-1|-1||
  45 NBus_Pin|pin@54||-16|-3|-1|-1||
  46 NWire_Pin|pin@55||18|-12||||
  47 NWire_Pin|pin@56||18|-9||||
  48 NWire_Pin|pin@57||6|-12||||
  49 NWire_Pin|pin@58||6|-15.5||||
  50 NWire_Pin|pin@59||18|-18||||
  51 NWire_Pin|pin@60||18|-15||||
  52 NWire_Pin|pin@61||6|-18||||
  53 NWire_Pin|pin@62||6|-21.5||||
  54 NWire_Pin|pin@63||-23.5|-12|||X|
  55 NWire_Pin|pin@64||-23.5|-9|||X|
  56 NWire_Pin|pin@65||-11.5|-12|||X|
  57 NWire_Pin|pin@66||-11.5|-15.5|||X|
  58 NWire_Pin|pin@67||-23.5|-18|||X|
  59 NWire_Pin|pin@68||-23.5|-15|||X|
  60 NWire_Pin|pin@69||-11.5|-18|||X|
  61 NWire_Pin|pin@70||-11.5|-21.5|||X|
  62 IorangeTSMC090nm:wire90;1{ic}|wire90@0||12.5|-12|||D0G4;|ATTR_L(D5G1;PUD)S2550|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  63 IorangeTSMC090nm:wire90;1{ic}|wire90@4||12.5|-18|||D0G4;|ATTR_L(D5G1;PUD)S2550|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  64 IorangeTSMC090nm:wire90;1{ic}|wire90@5||-18|-18|X||D0G4;|ATTR_L(D5G1;PUD)S2550|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  65 IorangeTSMC090nm:wire90;1{ic}|wire90@6||-18|-12|X||D0G4;|ATTR_L(D5G1;PUD)S2550|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  66 Abus|inA[1:18]|D5G2;|-0.5|IJ900|pin@18||16|-1|pin@19||16|-5
  67 Awire|inA[19]|D5G2;||900|pin@35||-7|-1|pin@36||-7|-4
  68 Abus|inA[20:37]|D5G2;|-0.5|IJ900|pin@49||-32|-1|pin@50||-32|-5
  69 Abus|inB[1:18]|D5G2;|-0.5|IJ2700|pin@24||16|1|pin@25||16|5
  70 Awire|inB[19]|D5G2;||2700|pin@33||-7|1|pin@34||-7|4
  71 Abus|inB[20:37]|D5G2;|-0.5|IJ2700|pin@51||-32|1|pin@52||-32|5
  72 Abus|net@20||-0.5|IJ0|data2in6@1|inA[1:18]|21|-1|pin@18||16|-1
  73 Abus|net@30||-0.5|IJ0|data2in6@1|inB[1:18]|21|1|pin@24||16|1
  74 Awire|net@39|||0|latch2in@4|inB[1]|-3|1|pin@33||-7|1
  75 Awire|net@41|||0|latch2in@4|inA[1]|-3|-1|pin@35||-7|-1
  76 Awire|net@47|||1800|latch2in@4|out[1]|3|0|pin@41||7|0
  77 Abus|net@48||-0.5|IJ900|pin@44||-2|-9|conn@2|y|-2|-13.5
  78 Abus|net@70||-0.5|IJ1800|data2in6@2|out[1:18]|-21|0|pin@53||-16|0
  79 Abus|net@73||-0.5|IJ0|data2in6@2|inA[1:18]|-27|-1|pin@49||-32|-1
  80 Abus|net@74||-0.5|IJ0|data2in6@2|inB[1:18]|-27|1|pin@51||-32|1
  81 Awire|net@75|||1800|wire90@0|b|15|-12|pin@55||18|-12
  82 Awire|net@77|||0|wire90@0|a|10|-12|pin@57||6|-12
  83 Awire|net@79|||1800|wire90@4|b|15|-18|pin@59||18|-18
  84 Awire|net@80|||0|wire90@4|a|10|-18|pin@61||6|-18
  85 Awire|net@83|||0|wire90@6|b|-20.5|-12|pin@63||-23.5|-12
  86 Awire|net@84|||1800|wire90@6|a|-15.5|-12|pin@65||-11.5|-12
  87 Awire|net@85|||0|wire90@5|b|-20.5|-18|pin@67||-23.5|-18
  88 Awire|net@86|||1800|wire90@5|a|-15.5|-18|pin@69||-11.5|-18
  89 Abus|net@90||-0.5|IJ1800|data2in6@1|out[1:18]|27|0|pin@39||31|0
  90 Abus|out[1:18]|D5G2;|-0.5|IJ900|pin@39||31|0|pin@40||31|-3
  91 Awire|out[19]|D5G2;||900|pin@41||7|0|pin@42||7|-3
  92 Abus|out[20:37]|D5G2;|-0.5|IJ900|pin@53||-16|0|pin@54||-16|-3
  93 Abus|take[A1,B1]|D5G2;|-0.5|IJ900|data2in6@2|dcl[A,B]|-26|-3|pin@43||-26|-9
  94 Awire|take[A1]|D5G2;||2700|pin@63||-23.5|-12|pin@64||-23.5|-9
  95 Abus|take[A2,B2]|D5G2;|-0.5|IJ2700|pin@45||22|-9|data2in6@1|dcl[A,B]|22|-3
  96 Awire|take[A2]|D5G2;||2700|pin@55||18|-12|pin@56||18|-9
  97 Awire|take[A]|D5G2;||900|latch2in@4|hcl[A]|-2|-3|pin@48||-2|-6
  98 Awire|take[A]|D5G2;||900|pin@57||6|-12|pin@58||6|-15.5
  99 Awire|take[A]|D5G2;||900|pin@65||-11.5|-12|pin@66||-11.5|-15.5
 100 Awire|take[B1]|D5G2;||2700|pin@67||-23.5|-18|pin@68||-23.5|-15
 101 Awire|take[B2]|D5G2;||2700|pin@59||18|-18|pin@60||18|-15
 102 Awire|take[B]|D5G2;||2700|latch2in@4|hcl[B]|-2|3|pin@47||-2|6
 103 Awire|take[B]|D5G2;||900|pin@61||6|-18|pin@62||6|-21.5
 104 Awire|take[B]|D5G2;||900|pin@69||-11.5|-18|pin@70||-11.5|-21.5
 105 EainA[1:14,TT]|inA[1:37]|D4G2;|conn@1|a|I
 106 EainB[1:14,TT]|inB[1:37]|D4G2;|conn@3|a|I
 107 Eaout[1:14,TT]|out[1:37]|D6G2;|conn@0|y|O
 108 Efire[A,B]|take[A,B]|D4G2;|conn@2|a|I
 109 X