chips/marina/electric/registersM.delib/dockPSreg.sch

   1 HregistersM|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 LloopCountM|loopCountM
   8
   9 LorangeTSMC090nm|orangeTSMC090nm
  10
  11 LredFive|redFive
  12
  13 LwiresL|wiresL
  14
  15 # Cell dockPSreg;2{sch}
  16 CdockPSreg;2{sch}||schematic|1234804637641|1240921669880|
  17 Ngeneric:Facet-Center|art@0||0|0||||AV
  18 NOff-Page|conn@0||-9|22|||RRR|
  19 NOff-Page|conn@1||-12|0||||
  20 NOff-Page|conn@2||9|0||||
  21 NOff-Page|conn@4||-31|10|||X|
  22 IdockPSreg;1{ic}|dockPSre@0||15.5|19.5|||D5G4;
  23 IredFive:inv;1{ic}|inv@0||-9|14|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S40|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
  24 IlatchesK:latch1in20B;1{ic}|lx[1:27]|D5G3;Y4.5;|0|0|Y||D5G4;
  25 IloopCountM:muxForPS;1{ic}|muxForOD@0||-23|10|X||D5G4;
  26 Ngeneric:Invisible-Pin|pin@0||0|53.5|||||ART_message(D5G5;)SdockPSreg
  27 Ngeneric:Invisible-Pin|pin@1||0.5|49.5|||||ART_message(D5G3;)Sies 15 March 2009
  28 NWire_Pin|pin@2||-9|6.5||||
  29 NBus_Pin|pin@5||-16|10|-1|-1||
  30 NBus_Pin|pin@6||-16|6|-1|-1||
  31 NWire_Pin|pin@7||-23|3||||
  32 Ngeneric:Invisible-Pin|pin@8||1.5|44.5|||||ART_message(D5G3;)S[reduced to 27 bit width,25 April 2009]
  33 NWire_Pin|pin@13||-2|6.5||||
  34 Ngeneric:Invisible-Pin|pin@15||-23.5|37.5|||||ART_message(D3G2;)S[The ps register holds the instruction being done.,It is normally transparent.,Goes opaque while doing instruction.]
  35 IwiresL:tranCap;1{ic}|tc[1:3]|D5G3;X2;Y2;|-22|22|||D5G4;
  36 IorangeTSMC090nm:wire90;1{ic}|wire90@0||-5.5|6.5|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D4446.400000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
  37 Awire|hold[1]|D5G2;||2700|lx[1:27]|hcl|-2|3|pin@13||-2|6.5
  38 Awire|net@1|||1800|pin@2||-9|6.5|wire90@0|a|-8|6.5
  39 Abus|net@11||-0.5|IJ1800|muxForOD@0|in[1:6]|-21|10|pin@5||-16|10
  40 Abus|net@13||-0.5|IJ0|muxForOD@0|out[1:7]|-26|10|conn@4|a|-29|10
  41 Awire|net@22|||1800|wire90@0|b|-3|6.5|pin@13||-2|6.5
  42 Awire|net@31|||900|inv@0|out|-9|11.5|pin@2||-9|6.5
  43 Abus|net@32||-0.5|IJ0|lx[1:27]|in[1]|-3|0|conn@1|y|-10|0
  44 Awire|net@33|||2700|inv@0|in|-9|16.5|conn@0|y|-9|20
  45 Abus|net@37||-0.5|IJ0|conn@2|a|7|0|lx[1:27]|out[1]|3|0
  46 Abus|ps[1:6,8]|D5G2;|-0.5|IJ900|pin@5||-16|10|pin@6||-16|6
  47 Awire|ps[20]|D5G2;||900|muxForOD@0|sel|-23|7|pin@7||-23|3
  48 Efire[1]|do[ins]|D4G2;|conn@0|a|I
  49 Em1[1:36]|m1[1:27]|D4G2;|conn@1|a|I
  50 EoutLO[1:7]||D6G2;|conn@4|y|O
  51 Eps[1:36]|ps[1:27]|D6G2;|conn@2|y|O
  52 X