chips/marina/electric/registersM.delib/ins1in20Bx18.sch

   1 HregistersM|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell ins1in20Bx18;1{sch}
   8 Cins1in20Bx18;1{sch}||schematic|1194187081843|1231452012341|I
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-9|0||||
  11 NOff-Page|conn@4||9|0||||
  12 NOff-Page|conn@7||-2|-9|||R|
  13 IlatchesK:latch1in20B;1{ic}|lx[1:18]|D5G3;Y4.5;|0|0|||D5G4;
  14 Ngeneric:Invisible-Pin|pin@0||-0.5|23.5|||||ART_message(D5G3;)Sies 30 December 2008
  15 Ngeneric:Invisible-Pin|pin@1||-1.5|31.5|||||ART_message(D5G4;)S[eighteen 20B latches,in one row for the Dock's Ring]
  16 Ngeneric:Invisible-Pin|pin@2||0.5|39|||||ART_message(D5G6;)Sins1in20Bx18
  17 Ngeneric:Invisible-Pin|pin@3||-1.5|17.5|||||ART_message(D5G2;)S[bit arrangement:,01 18 02 17 03 16 04 15 05 14 06 13 07 12 08 11 09 10]
  18 Iins1in20Bx18;1{ic}|short20B@0||20|9.5|||D5G4;
  19 Awire|net@114|||2700|conn@7|y|-2|-7|lx[1:18]|hcl|-2|-3
  20 Abus|net@116||-0.5|IJ1800|lx[1:18]|out[1]|3|0|conn@4|a|7|0
  21 Abus|net@136||-0.5|IJ0|lx[1:18]|in[1]|-3|0|conn@0|y|-7|0
  22 Ehcl[1]|hcl|D4G2;|conn@7|a|I
  23 Ein[1:18]||D4G2;|conn@0|a|I
  24 Eout[1:18]||D6G2;|conn@4|y|O
  25 X