chips/marina/electric/registersM.delib/ins2in20Ax18.sch

   1 HregistersM|8.10k
   2
   3 # External Libraries:
   4
   5 LlatchesK|latchesK
   6
   7 # Cell ins2in20Ax18;1{sch}
   8 Cins2in20Ax18;1{sch}||schematic|1194187081843|1231451816788|I
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-9|-2||||
  11 NOff-Page|conn@4||9|0||||
  12 NOff-Page|conn@7||-2|-9|||R|
  13 NOff-Page|conn@8||-9|2||||
  14 NOff-Page|conn@9||-2|9|||RRR|
  15 IlatchesK:latch2in20A;1{ic}|lx[1:18]|D5G3;Y4.5;|0|0|||D5G4;
  16 Ngeneric:Invisible-Pin|pin@0||-0.5|24.5|||||ART_message(D5G3;)Sies 31 December 2008
  17 Ngeneric:Invisible-Pin|pin@1||-1.5|31.5|||||ART_message(D5G4;)S[eighteen 20A latches,in one row]
  18 Ngeneric:Invisible-Pin|pin@2||1.5|40.5|||||ART_message(D5G6;)Sins2in20Ax18
  19 NBus_Pin|pin@3||-5|2|-1|-1||
  20 NBus_Pin|pin@4||-5|1|-1|-1||
  21 NBus_Pin|pin@5||-5|-2|-1|-1||
  22 NBus_Pin|pin@6||-5|-1|-1|-1||
  23 Ngeneric:Invisible-Pin|pin@7||-0.5|19|||||ART_message(D5G2;)S[bit arrangement:,01 18 02 17 03 16 04 15 05 14 06 13 07 12 08 11 09 10]
  24 Iins2in20Ax18;1{ic}|short2in@0||20|9.5|||D5G4;
  25 Awire|net@114|||2700|conn@7|y|-2|-7|lx[1:18]|hcl[A]|-2|-3
  26 Abus|net@116||-0.5|IJ1800|lx[1:18]|out[1]|3|0|conn@4|a|7|0
  27 Abus|net@139||-0.5|IJ1800|conn@8|y|-7|2|pin@3||-5|2
  28 Abus|net@140||-0.5|IJ900|pin@3||-5|2|pin@4||-5|1
  29 Abus|net@141||-0.5|IJ1800|pin@4||-5|1|lx[1:18]|inB[1]|-3|1
  30 Abus|net@142||-0.5|IJ1800|conn@0|y|-7|-2|pin@5||-5|-2
  31 Abus|net@143||-0.5|IJ2700|pin@5||-5|-2|pin@6||-5|-1
  32 Abus|net@144||-0.5|IJ1800|pin@6||-5|-1|lx[1:18]|inA[1]|-3|-1
  33 Awire|net@145|||900|conn@9|y|-2|7|lx[1:18]|hcl[B]|-2|3
  34 Ehcl[A][1]|hcl[A]|D4G2;|conn@7|a|I
  35 Ehcl[B][1]|hcl[B]|D4G2;|conn@9|a|I
  36 EinA[1:18]||D4G2;|conn@0|a|I
  37 EinB[1:18]||D4G2;|conn@8|a|I
  38 Eout[1:18]||D6G2;|conn@4|y|O
  39 X