migrate jelib->delib
[fleet.git] / chips / marina / electric / scanM.delib / scanTwinAmpPair.lay
1 HscanM|8.10k
2
3 # External Libraries:
4
5 LwiresL|wiresL
6
7 # Cell scanTwinAmpPair;1{lay}
8 CscanTwinAmpPair;1{lay}||cmos90|1196125119543|1243341551766|I|ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
9 Ngeneric:Facet-Center|art@0||0|0||||AV
10 IscanTwinAmp;3{lay}|scanTwin@2||44|0|||D5G4;
11 IscanTwinAmp;3{lay}|scanTwin@3||-44|0|X||D5G4;
12 IwiresL:wellContacts26;1{lay}|wellCont@1||0|0|||D5G4;
13 Ametal-2|net@4||6.2|S1800|wellCont@1|gnd_1|4.5|0|scanTwin@2|gnd|11.5|0
14 Ametal-2|net@5||6.2|S1800|wellCont@1|vdd_2|4.5|-50|scanTwin@2|vdd_9|11.5|-50
15 Ametal-2|net@6||6.2|S1800|wellCont@1|vdd_3|4.5|50|scanTwin@2|vdd|11.5|50
16 Ametal-2|net@7||6.2|S1800|scanTwin@3|vdd|-11.5|50|wellCont@1|vdd_1|-4.5|50
17 Ametal-2|net@8||6.2|S0|wellCont@1|gnd|-4.5|0|scanTwin@3|gnd|-11.5|0
18 Ametal-2|net@9||6.2|S0|wellCont@1|vdd|-4.5|-50|scanTwin@3|vdd_9|-11.5|-50
19 Egnd_3||D5G2;|scanTwin@3|gnd_3|G
20 Egnd_4||D5G2;|scanTwin@2|gnd_3|G
21 Ein[1]||D5G2;|scanTwin@3|in[1]|I
22 Ein[2]||D5G2;|scanTwin@2|in[1]|I
23 EoutA[1]||D5G2;|scanTwin@3|outA[1]|O
24 EoutA[2]||D5G2;|scanTwin@2|outA[1]|O
25 EoutB[1]||D5G2;|scanTwin@3|outB[1]|O
26 EoutB[2]||D5G2;|scanTwin@2|outB[1]|O
27 Evdd_6||D5G2;|scanTwin@3|vdd_6|P
28 Evdd_7||D5G2;|scanTwin@3|vdd_7|P
29 Evdd_8||D5G2;|scanTwin@2|vdd_6|P
30 Evdd_9||D5G2;|scanTwin@2|vdd_7|P
31 X