chips/marina/electric/stageGroupsM.delib/properStopper.sch

   1 HstageGroupsM|8.10k
   2
   3 # External Libraries:
   4
   5 LorangeTSMC090nm|orangeTSMC090nm
   6
   7 LstagesM|stagesM
   8
   9 # Cell properStopper;1{sch}
  10 CproperStopper;1{sch}||schematic|1182121322015|1243246708862|I
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 NOff-Page|conn@1||-21|-7|||Y|
  13 NOff-Page|conn@2||22|-7||||
  14 NOff-Page|conn@4||-21|9|||Y|
  15 NOff-Page|conn@5||-21|2|||Y|
  16 NOff-Page|conn@6||-21|6|||Y|
  17 NOff-Page|conn@7||22|6||||
  18 NOff-Page|conn@8||22|2||||
  19 NOff-Page|conn@9||22|9||||
  20 NOff-Page|conn@10||22|12||||
  21 NOff-Page|conn@11||-21|12|||Y|
  22 NOff-Page|conn@14||-3|-2.5||||
  23 NOff-Page|conn@15||-12|-13|||RRR|
  24 IstagesM:drainStage;1{ic}|drainSta@1||12|0|||D5G4;
  25 IstagesM:fillStage;1{ic}|fillStag@1||-12|0|||D5G4;
  26 Ngeneric:Invisible-Pin|pin@3||-12|41|||||ART_message(D5FLeave alone;G5;)SproperStopper
  27 Ngeneric:Invisible-Pin|pin@4||-10.5|33|||X||ART_message(D5FLeave alone;G3;)Sies 21 February 2009
  28 Ngeneric:Invisible-Pin|pin@5||-10|29|||||ART_message(D5FLeave alone;G2;)SA complete pair to load and unload
  29 Ngeneric:Invisible-Pin|pin@6||-22.5|24.5|||||ART_message(D3G2;)S[layout for control in center,and m2 ports,ies 21 February 2009]
  30 IproperStopper;1{ic}|properSt@0||23.5|29|||D5G4;
  31 IorangeTSMC090nm:wire90;1{ic}|wire90@0||1|2|||D0G4;|ATTR_L(D5G1;PUD)D2080.3999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
  32 Abus|net@2||-0.5|IJ1800|fillStag@1|sor[1:9]|-10|6|drainSta@1|sir[1:9]|11|6
  33 Abus|net@3||-0.5|IJ1800|fillStag@1|soc[1:9]|-10|9|drainSta@1|sic[1:9]|11|9
  34 Abus|net@4||-0.5|IJ1800|conn@1|y|-19|-7|fillStag@1|in[1:37],ain[T,1:14]|-14|-7
  35 Abus|net@6||-0.5|IJ1800|drainSta@1|out[1:37],aout[T,1:14]|14|-7|conn@2|a|20|-7
  36 Abus|net@10||-0.5|IJ0|fillStag@1|sir[1:9]|-13|6|conn@6|y|-19|6
  37 Abus|net@15||-0.5|IJ1800|drainSta@1|sor[1:9]|14|6|conn@7|a|20|6
  38 Abus|net@16||-0.5|IJ1800|drainSta@1|soc[1:9]|14|9|conn@9|a|20|9
  39 Abus|net@18||-0.5|IJ0|fillStag@1|sic[1:9]|-13|9|conn@4|y|-19|9
  40 Awire|net@19|||0|fillStag@1|pred|-14|2|conn@5|y|-19|2
  41 Awire|net@20|||1800|drainSta@1|succ|14|2|conn@8|a|20|2
  42 Abus|net@21||-0.5|IJ1800|conn@11|y|-19|12|fillStag@1|sid[1:9]|-13|12
  43 Abus|net@22||-0.5|IJ1800|fillStag@1|sod[1:9]|-10|12|conn@10|a|20|12
  44 Awire|net@41|||1800|fillStag@1|succ|-10|2|wire90@0|a|-1.5|2
  45 Awire|net@42|||1800|wire90@0|b|3.5|2|drainSta@1|pred|10|2
  46 Abus|net@65||-0.5|IJ1800|fillStag@1|out[1:37],aout[T,1:14]|-10|-7|drainSta@1|in[1:37],ain[T,1:14]|10|-7
  47 Awire|net@66|||0|conn@14|a|-5|-2.5|fillStag@1|fire_1|-9|-2.5
  48 Awire|net@69|||2700|conn@15|a|-12|-11|fillStag@1|succ_1|-12|-9
  49 Ein[1:37],ain[T,1:14]|ain[TT,1:14],in[1:37]|D4G3;|conn@1|a|I
  50 Eout[1:37],aout[T,1:14]|aout[TT,1:14],out[1:37]|D6G3;|conn@2|y|O
  51 Eextra||D6G2;|conn@14|y|O
  52 Efire||D6G2;|conn@15|y|O
  53 Epred||D4G3;|conn@5|a|I
  54 Esic[1:9]||D4G3;|conn@4|a|B
  55 Esid[1:9]||D4G3;|conn@11|a|B
  56 Esir[1:9]||D4G3;|conn@6|a|B
  57 Esoc[1:9]||D6G3;|conn@9|y|B
  58 Esod[1:9]||D6G3;|conn@10|y|B
  59 Esor[1:9]||D6G3;|conn@7|y|B
  60 Esucc||D6G3;|conn@8|y|O
  61 X