chips/marina/electric/stagesM.delib/litDandP.sch

   1 HstagesM|8.10k
   2
   3 # External Libraries:
   4
   5 LgaspM|gaspM
   6
   7 LlatchesK|latchesK
   8
   9 LorangeTSMC090nm|orangeTSMC090nm
  10
  11 LregistersM|registersM
  12
  13 LwiresL|wiresL
  14
  15 # Cell litDandP;3{sch}
  16 ClitDandP;3{sch}||schematic|1234735235714|1243246708862|I
  17 Ngeneric:Facet-Center|art@0||0|0||||AV
  18 IwiresL:bitAssignments;1{ic}|bitAssig@0||67|13|||D5G4;
  19 NOff-Page|conn@2||49|12||||
  20 NOff-Page|conn@6||24|23|||RRR|
  21 NOff-Page|conn@8||-5.5|14|||Y|
  22 NOff-Page|conn@9||18|-22.5||||
  23 NOff-Page|conn@10||-12.5|-15||||
  24 NOff-Page|conn@11||-16.5|-20.5|||XRR|
  25 NWire_Con|conn@16||37|-16.5||||
  26 NOff-Page|conn@17||59|0||||
  27 NOff-Page|conn@18||39.5|1|||Y|
  28 IgaspM:gaspLit;2{ic}|gaspLit@1||0|12|||D5G4;
  29 IlatchesK:latch2in60C;1{ic}|latch2in@0||50|0|||D5G4;
  30 IlitDandP;1{ic}|litDockS@0||62.5|40|||D5G4;
  31 IlitDrivers;1{ic}|litDrive@0||24|12|||D5G4;
  32 IregistersM:newDregister;1{ic}|newDregi@0||2|-18|Y||D5G4;
  33 IregistersM:newPathReg;1{ic}|newPathR@0||1.5|-31.5|Y||D5G4;
  34 Ngeneric:Invisible-Pin|pin@0||3|55.5|||||ART_message(D5G6;)SlitDandP
  35 Ngeneric:Invisible-Pin|pin@1||1.5|41|||||ART_message(D5G3;)Sies 9 May 2009
  36 Ngeneric:Invisible-Pin|pin@2||2.5|47.5|||||ART_message(D5G3;)S["Here are the drivers for the D register,","the D register itself, and the path register"]
  37 NBus_Pin|pin@11||0|-8|-1|-1||
  38 NWire_Pin|pin@15||0|3||||
  39 NWire_Pin|pin@41||20|4|||X|
  40 NBus_Pin|pin@46||-6|-19|-1|-1||
  41 NBus_Pin|pin@48||-6|-17|-1|-1||
  42 NBus_Pin|pin@56||37|-20.5|-1|-1||
  43 NBus_Pin|pin@57||37|-12.5|-1|-1||
  44 NWire_Pin|pin@59||43.5|-1||||
  45 NWire_Pin|pin@60||43.5|-6||||
  46 NWire_Pin|pin@61||48|-5.5||||
  47 NBus_Pin|pin@66||-6|-13|-1|-1||
  48 Ngeneric:Invisible-Pin|pin@67||74.5|10.5|||||ART_message(D3G2;)S["flag[C] loaded from data","predecessor bonus bit ps[B]",or from xxx (from where?),on moves that don't capture,data.]
  49 Ngeneric:Invisible-Pin|pin@69||48.5|21.5|||||ART_message(D3G2;)Ssel[Do] is called use[Do] in move logic
  50 NBus_Pin|pin@73||-8.5|-25.5|-1|-1|Y|
  51 NBus_Pin|pin@74||-8.5|-30.5|-1|-1|Y|
  52 NBus_Pin|pin@75||-8.5|-37.5|-1|-1|Y|
  53 NBus_Pin|pin@76||-8.5|-32.5|-1|-1|Y|
  54 NBus_Pin|pin@77||11.5|-31.5|-1|-1|Y|
  55 NBus_Pin|pin@78||11.5|-26.5|-1|-1||
  56 NBus_Pin|pin@79||11|-18|-1|-1||
  57 NBus_Pin|pin@80||11|-13|-1|-1||
  58 NWire_Pin|pin@81||-0.5|-24.5||||
  59 NWire_Pin|pin@83||-12|10||||
  60 NWire_Pin|pin@84||-12|8||||
  61 NBus_Pin|pin@85||-6|-23|-1|-1||
  62 NBus_Pin|pin@107||24|0|-1|-1||
  63 NWire_Pin|pin@108||48|6||||
  64 NWire_Pin|pin@109||28|6||||
  65 IwiresL:tranCap;1{ic}|tc[1:11]|D5G3;X2;Y2;|-23|34|||D5G4;
  66 IorangeTSMC090nm:wire90;1{ic}|wire90@1||11.5|12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D402.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
  67 IorangeTSMC090nm:wire90;1{ic}|wire90@4||38.5|6|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D402.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
  68 Abus|dp[1:37]|D5G2;|-0.5|IJ2700|pin@48||-6|-17|pin@66||-6|-13
  69 Abus|dp[26:37]|D5G2;|-0.5|IJ900|pin@73||-8.5|-25.5|pin@74||-8.5|-30.5
  70 Awire|dp[B]|D5G2;||900|pin@59||43.5|-1|pin@60||43.5|-6
  71 Abus|dsA[TT,1:14]|D5G2;|-0.5|IJ2700|pin@77||11.5|-31.5|pin@78||11.5|-26.5
  72 Abus|dsD[1:37]|D5G2;|-0.5|IJ2700|pin@79||11|-18|pin@80||11|-13
  73 Awire|fire[M]|D5G2;||2700|newPathR@0|fire[A,B]|-0.5|-28.5|pin@81||-0.5|-24.5
  74 Abus|net@60||-0.5|IJ1800|pin@46||-6|-19|newDregi@0|inB[1:37]|-1|-19
  75 Abus|net@63||-0.5|IJ1800|pin@48||-6|-17|newDregi@0|inA[1:37]|-1|-17
  76 Awire|net@78|||0|latch2in@0|inA[1]|47|-1|pin@59||43.5|-1
  77 Awire|net@84|||0|conn@17|a|57|0|latch2in@0|out[1]|53|0
  78 Awire|net@90|||0|latch2in@0|inB[1]|47|1|conn@18|y|41.5|1
  79 Abus|net@95||-0.5|IJ1800|newPathR@0|aout[1:14,TT]|4.5|-31.5|pin@77||11.5|-31.5
  80 Abus|net@96||-0.5|IJ1800|pin@76||-8.5|-32.5|newPathR@0|ainB[1:14,TT]|-1.5|-32.5
  81 Abus|net@97||-0.5|IJ1800|pin@74||-8.5|-30.5|newPathR@0|ainA[1:14,TT]|-1.5|-30.5
  82 Abus|net@98||-0.5|IJ1800|newDregi@0|out[1:37]|5|-18|pin@79||11|-18
  83 Awire|net@104|||1800|conn@8|y|-3.5|14|gaspLit@1|do[ins]|-3|14
  84 Awire|net@106|||0|gaspLit@1|sel[Lt]|-3|10|pin@83||-12|10
  85 Awire|net@108|||0|wire90@1|a|9|12|gaspLit@1|ready|3|12
  86 Awire|net@130|||0|litDrive@0|ready|18|12|wire90@1|b|14|12
  87 Abus|net@136||-0.5|IJ1800|litDrive@0|succ[D,T]|30|12|conn@2|a|47|12
  88 Awire|net@137|||900|conn@6|y|24|21|litDrive@0|fire[M]|24|17
  89 Awire|net@140|||0|pin@108||48|6|wire90@4|b|41|6
  90 Awire|net@141|||2700|pin@109||28|6|litDrive@0|take[C]|28|8
  91 Awire|net@142|||2700|latch2in@0|hcl[B]|48|3|pin@108||48|6
  92 Awire|net@146|||0|wire90@4|a|36|6|pin@109||28|6
  93 Abus|ps[1:15]|D5G2;|-0.5|IJ2700|pin@75||-8.5|-37.5|pin@76||-8.5|-32.5
  94 Abus|ps[1:20]|D5G2;|-0.5|IJ900|pin@46||-6|-19|pin@85||-6|-23
  95 Abus|ps[27,17,16,15]|D5G2;|-0.5|IJ900|conn@16||37|-16.5|pin@56||37|-20.5
  96 Abus|sel[Dc,Do,To]|D5G2;|-0.5|IJ900|litDrive@0|sel[Dc,Do,To]|24|7|pin@107||24|0
  97 Abus|sel[Lt,Dc,Do,To]|D5G2;|-0.5|IJ2700|conn@16||37|-16.5|pin@57||37|-12.5
  98 Awire|sel[Lt]|D5G2;||900|pin@83||-12|10|pin@84||-12|8
  99 Abus|take[A,B]|D5G2;|-0.5|IJ2700|newDregi@0|take[A,B]|0|-15|pin@11||0|-8
 100 Awire|take[A]|D5G2;||900|latch2in@0|hcl[A]|48|-3|pin@61||48|-5.5
 101 Awire|take[A]|D5G2;||900|litDrive@0|take[A]|20|8|pin@41||20|4
 102 Awire|take[B]|D5G2;||900|gaspLit@1|fire[L]|0|8|pin@15||0|3
 103 Edo[ins]||D4G2;|conn@8|a|I
 104 Edp[1:37,B]||D4G2;|conn@10|a|I
 105 EdsA[TT,1:14],dsD[1:37]||D6G2;|conn@9|y|O
 106 Efire[M]||D4G2;|conn@6|a|I
 107 Eflag[C]||D6G2;|conn@17|y|O
 108 Eps[1:20,27]||D4G2;|conn@11|a|I
 109 EsignalBitFromInboundSwitchFabric||D4G2;|conn@18|a|I
 110 Esucc[D,T]||D6G2;|conn@2|y|O
 111 X