chips/marina/electric/stagesM.delib/weakStage.sch

   1 HstagesM|8.10k
   2
   3 # External Libraries:
   4
   5 LgaspM|gaspM
   6
   7 LregistersM|registersM
   8
   9 LscanM|scanM
  10
  11 LwiresL|wiresL
  12
  13 # Cell weakStage;1{sch}
  14 CweakStage;1{sch}||schematic|1195254411267|1238782566350|I|ATTR_FLAG(D5G2;NTX-1;Y42;)S[atomic]
  15 IregistersM:addr1in20Bx15;1{ic}|addr1in2@0||0|-12|Y||D5G4;
  16 Ngeneric:Facet-Center|art@0||0|0||||AV
  17 NOff-Page|conn@0||29|-9||||
  18 NOff-Page|conn@1||-13|-9||||
  19 NOff-Page|conn@2||9|4||||
  20 NOff-Page|conn@3||-8.5|4||||
  21 NOff-Page|conn@4||-5.5|18||||
  22 NOff-Page|conn@6||10|18||||
  23 IregistersM:data1in20Bx37;1{ic}|data1in2@0||20|-18|Y||D5G4;
  24 IgaspM:gaspWeak;1{ic}|gaspWeak@0||0|0|||D5G4;
  25 Ngeneric:Invisible-Pin|pin@0||0.5|55.5|||||ART_message(D5G6;)SweakStage
  26 Ngeneric:Invisible-Pin|pin@2||-1.5|50.5|||||ART_message(D5G4;)Sthe plain stage w/small latches
  27 Ngeneric:Invisible-Pin|pin@11||-11.5|32.5|||||ART_message(D3G2;)S[layout for control in middle,and scan on right]
  28 NWire_Pin|pin@12||3|24||||
  29 NWire_Pin|pin@13||-2|24||||
  30 NWire_Pin|pin@15||18|-9||||
  31 NWire_Pin|pin@16||2|-9||||
  32 NBus_Pin|pin@17||-9|-12|-1|-1||
  33 NBus_Pin|pin@18||-9|-16|-1|-1||
  34 NBus_Pin|pin@19||9|-12|-1|-1||
  35 NBus_Pin|pin@20||9|-17|-1|-1||
  36 NBus_Pin|pin@21||11|-18|-1|-1||
  37 NBus_Pin|pin@22||11|-22.5|-1|-1||
  38 NBus_Pin|pin@23||27.5|-18|-1|-1||
  39 NBus_Pin|pin@24||27.5|-22|-1|-1||
  40 NWire_Pin|pin@25||-9.5|0||||
  41 NWire_Pin|pin@26||-9.5|-5||||
  42 Ngeneric:Invisible-Pin|pin@27||-12.5|39.5|||||ART_message(D3G2;)S[up and down forms,differ in scan chain direction]
  43 Ngeneric:Invisible-Pin|pin@28||-0.5|46.5|||||ART_message(D5FLeave alone;G3;)Sies 3 April 2009
  44 IweakStageDN;1{ic}|plainSta@0||33|9|||D5G4;
  45 IscanM:scanEx1;1{ic}|scanEx1@0||4|18|XR||D5G4;
  46 IwiresL:tranCap;1{ic}|tc[1:9]|D5G3;X2;Y2;|-21|26|||D5G4;
  47 IweakStageUP;2{ic}|weakStag@0||33|31|||D5G4;
  48 Abus|ain[TT,1:14]|D5G2;|-0.5|IJ900|pin@17||-9|-12|pin@18||-9|-16
  49 Awire|ain[TT]|D5G2;||900|pin@25||-9.5|0|pin@26||-9.5|-5
  50 Abus|aout[TT,1:14]|D5G2;|-0.5|IJ900|pin@19||9|-12|pin@20||9|-17
  51 Abus|in[1:37]|D5G2;|-0.5|IJ900|pin@21||11|-18|pin@22||11|-22.5
  52 Awire|net@37|||0|gaspWeak@0|pred|-3|4|conn@3|y|-6.5|4
  53 Awire|net@38|||1800|gaspWeak@0|succ|3|4|conn@2|a|7|4
  54 Awire|net@39|||900|scanEx1@0|dIn[1]|2|13|gaspWeak@0|s[1]|2|8
  55 Awire|net@40|||2700|scanEx1@0|mc|3|23|pin@12||3|24
  56 Awire|net@41|||0|pin@12||3|24|pin@13||-2|24
  57 Awire|net@42|||900|pin@13||-2|24|gaspWeak@0|mc|-2|7
  58 Abus|net@43||-0.5|IJ1800|conn@4|y|-3.5|18|scanEx1@0|sir[1:9]|2|18
  59 Abus|net@44||-0.5|IJ1800|scanEx1@0|sor[1:9]|6|18|conn@6|a|8|18
  60 Awire|net@47|||2700|data1in2@0|take|18|-15|pin@15||18|-9
  61 Awire|net@48|||0|pin@15||18|-9|pin@16||2|-9
  62 Awire|net@49|||2700|pin@16||2|-9|gaspWeak@0|take|2|-7
  63 Abus|net@50||-0.5|IJ0|addr1in2@0|ain[TT,1:14]|-3|-12|pin@17||-9|-12
  64 Abus|net@52||-0.5|IJ1800|addr1in2@0|aout[TT,1:14]|3|-12|pin@19||9|-12
  65 Abus|net@54||-0.5|IJ0|data1in2@0|in[1:37]|17|-18|pin@21||11|-18
  66 Abus|net@56||-0.5|IJ1800|data1in2@0|out[1:37]|23|-18|pin@23||27.5|-18
  67 Awire|net@58|||0|gaspWeak@0|tok|-3|0|pin@25||-9.5|0
  68 Awire|net@59|||2700|addr1in2@0|fire|-2|-9|gaspWeak@0|fire|-2|-7
  69 Abus|out[1:37]|D5G2;|-0.5|IJ900|pin@23||27.5|-18|pin@24||27.5|-22
  70 Ein[1:37],ain[T,1:14]|ain[TT,1:14],in[1:37]|D4G2;|conn@1|a|I
  71 Eout[1:37],aout[T,1:14]|aout[TT,1:14],out[1:37]|D6G2;|conn@0|y|O
  72 Epred||D4G2;|conn@3|a|I
  73 Esir[1:9]||D4G2;X-4;|conn@4|y|B
  74 Esor[1:9]||D6G2;|conn@6|y|B
  75 Esucc||D6G2;|conn@2|y|O
  76 X