chips/marina/electric/wiresL.delib/pinsVddGnd.lay

   1 HwiresL|8.10k
   2
   3 # Cell pinsVddGnd;1{lay}
   4 CpinsVddGnd;1{lay}||cmos90|1180462114023|1241981698008|I|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1242253744604|FACET_characteristic_spacing()D[0.0,144.0]
   5 Ngeneric:Facet-Center|art@0||0|0||||AV
   6 NMetal-2-Pin|pin@0||0|50|||Y|
   7 NMetal-2-Pin|pin@1||0|0|||Y|
   8 NMetal-2-Pin|pin@2||0|-50|||Y|
   9 Egnd||D5G2;|pin@1||G
  10 Evdd||D5G2;|pin@0||P
  11 Evdd_1||D5G2;|pin@2||P
  12 X