1 Marina Known Hardware Defficiencies
3 1) The signal OLC==0 isn't passed from On Deck stage to Requeue stage.
7 2) The external zero detector for loading the OLC and the ILC is too
8 slow. When the set instruction loads a nonzero value into the OLC or
9 the ILC Marina behaves as if the value is zero.
13 3) After the ILC decrements to zero, subsequent move instructions fail
14 to execute at all. According to adm33 subsequent move instructions are
15 supposed to execute exactly once.
19 4) When a move instruction is torpedoed, the following instruction
20 doesn't detect that the OLC is now zero.
24 5) The C flag is not yet implemented.
28 6) In gaspL:rqStage{sch}, a torpedo resets the OLC to zero asynchronously
29 with respect to the fireR. There may be a metastability problem here.
33 7) In fifoL:splitStart{sch} When the FIFO fills up and succA is asserted
34 but not acknowledged, the alternator will assert succB and overwrite the
39 8) Sense of Token bit in EPI FIFO is wrong. The correct sense is "High
44 9) EPI FIFO is missing it's data latches.