migrate jelib->delib
[fleet.git] / chips / omegaCounter / 40nm / electric / omegaCounter-old.delib / fakeForDRC.lay
1 HomegaCounter-old|8.10k
2
3 # Cell fakeForDRC;1{lay}
4 CfakeForDRC;1{lay}|oneCell|tsmcSun40GP|1250309607249|1250370709293||ATTR_NCC(D5G10;NTX-360;Y618.75;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/","exportsConnectedByParent disableLO /disableLO_[0-9]+/","exportsConnectedByParent disable /disable_[0-9]+/"]
5 Ngeneric:Facet-Center|art@0||0|0||||AV
6 IoneCell;1{lay}|oneCell@0||1.5|-164.5|R||D5G4;
7 ELSN[OneOrDone]||D5G2;|oneCell@0|LSN[OneOrDone]|B
8 ELSN[OneOrTwo]||D5G2;|oneCell@0|LSN[OneOrTwo]|B
9 EMSN[OneOrDone]||D5G2;|oneCell@0|MSN[OneOrDone]|B
10 EMSN[OneOrTwo]||D5G2;|oneCell@0|MSN[OneOrTwo]|B
11 Egnd||D5G2;|oneCell@0|gnd|G
12 Egnd_1||D5G2;|oneCell@0|gnd_1|G
13 Egnd_2||D5G2;|oneCell@0|gnd_2|G
14 Egnd_3||D5G2;|oneCell@0|gnd_3|G
15 Egnd_4||D5G2;|oneCell@0|gnd_4|G
16 Egnd_5||D5G2;|oneCell@0|gnd_5|G
17 Egnd_6||D5G2;|oneCell@0|gnd_6|G
18 Egnd_16||D5G2;|oneCell@0|gnd_16|U
19 Egnd_17||D5G2;|oneCell@0|gnd_17|U
20 Egnd_18||D5G2;|oneCell@0|gnd_18|U
21 Egnd_19||D5G2;|oneCell@0|gnd_19|U
22 Egnd_21||D5G2;|oneCell@0|gnd_21|U
23 Egnd_22||D5G2;|oneCell@0|gnd_22|U
24 Egnd_24||D5G2;|oneCell@0|gnd_24|U
25 Egnd_28||D5G2;|oneCell@0|gnd_28|U
26 Egnd_29||D5G2;|oneCell@0|gnd_29|G
27 Egnd_30||D5G2;|oneCell@0|gnd_30|G
28 Egnd_31||D5G2;|oneCell@0|gnd_31|G
29 Eload||D5G2;|oneCell@0|load|I
30 EloadLO||D5G2;|oneCell@0|loadLO|I
31 EloadLO_1||D5G2;|oneCell@0|disableLO_5|I
32 EloadLO_2||D5G2;|oneCell@0|disableLO_2|I
33 EloadLO_3||D5G2;|oneCell@0|loadLO_3|I
34 EloadLO_4||D5G2;|oneCell@0|loadLO_4|I
35 Eload_1||D5G2;|oneCell@0|disable_2|I
36 Eload_2||D5G2;|oneCell@0|disable_3|I
37 Eload_3||D5G2;|oneCell@0|disable_1|I
38 Eload_4||D5G2;|oneCell@0|load_4|I
39 Es[1]||D5G2;|oneCell@0|s[1]|O
40 Es[2]||D5G2;|oneCell@0|s[2]|O
41 EvalLO||D5G2;|oneCell@0|valLO|I
42 Evdd||D5G2;|oneCell@0|vdd|P
43 Evdd_1||D5G2;|oneCell@0|vdd_1|P
44 Evdd_2||D5G2;|oneCell@0|vdd_2|P
45 Evdd_3||D5G2;|oneCell@0|vdd_3|P
46 Evdd_4||D5G2;|oneCell@0|vdd_4|P
47 Evdd_5||D5G2;|oneCell@0|vdd_5|P
48 Evdd_6||D5G2;|oneCell@0|vdd_6|P
49 Evdd_10||D5G2;|oneCell@0|vdd_10|U
50 Evdd_11||D5G2;|oneCell@0|vdd_11|U
51 Evdd_12||D5G2;|oneCell@0|vdd_12|U
52 Evdd_13||D5G2;|oneCell@0|vdd_13|U
53 Evdd_14||D5G2;|oneCell@0|vdd_14|U
54 Evdd_16||D5G2;|oneCell@0|vdd_16|U
55 Evdd_17||D5G2;|oneCell@0|vdd_17|U
56 Evdd_25||D5G2;|oneCell@0|vdd_25|P
57 Evdd_26||D5G2;|oneCell@0|vdd_26|P
58 Evdd_27||D5G2;|oneCell@0|vdd_27|P
59 X