migrate jelib->delib
[fleet.git] / chips / omegaCounter / 40nm / electric / omegaCounter.delib / oneCell.ic
1 HomegaCounter|8.10k
2
3 # Cell oneCell;1{ic}
4 ConeCell;1{ic}||artwork|1242938717727|1254097708184|E|ATTR_LOAD_DRIVER_SIZE(D5G1;HNOLP)S8
5 Ngeneric:Facet-Center|art@0||0|0||||AV
6 NTriangle|art@8||-12|-5.5|3|2|XR|
7 NTriangle|art@9||-12|2.5|3|2|XR|
8 NThick-Circle|art@12||-10.5|-12|2|2|X|
9 NArrow|art@13||-3|-14|2|2|XR|
10 NArrow|art@14||-10.5|-14|2|2|XR|
11 NPin|pin@0||-1|10|1|1|X|
12 NPin|pin@1||-1|-14|1|1|X|
13 NPin|pin@2||-13|-14|1|1|X|
14 NPin|pin@3||-13|10|1|1|X|
15 Nschematic:Wire_Pin|pin@13||-1|2.5|||X|
16 Nschematic:Wire_Pin|pin@15||-3.5|10|||X|
17 Nschematic:Wire_Pin|pin@17||-13|2.5|||X|
18 Nschematic:Wire_Pin|pin@19||-13|-5.5|||X|
19 Nschematic:Wire_Pin|pin@20||-1|-5.5|||X|
20 NPin|pin@22||-1|2.5|1|1|X|
21 NPin|pin@24||-1|-5.5|1|1|X|
22 Nschematic:Bus_Pin|pin@73||-10|11|-1|-1||
23 Nschematic:Bus_Pin|pin@76||-10|10|-1|-1||
24 Nschematic:Wire_Pin|pin@78||-3|-14||||
25 Nschematic:Bus_Pin|pin@80||-10.5|-14||||
26 Nschematic:Bus_Pin|pin@81||-11.5|-14.5||||
27 Nschematic:Wire_Pin|pin@82||-11.5|-12.5||||
28 Nschematic:Bus_Pin|pin@83||-6.5|-14||||
29 Nschematic:Bus_Pin|pin@84||-7|10||||
30 ASolid|net@0|||FS900|pin@0||-1|10|pin@1||-1|-14
31 ASolid|net@1|||FS0|pin@1||-1|-14|pin@2||-13|-14
32 ASolid|net@2|||FS2700|pin@2||-13|-14|pin@3||-13|10
33 ASolid|net@3|||FS1800|pin@3||-13|10|pin@0||-1|10
34 Aschematic:bus|net@23||-0.5|IJ900|pin@73||-10|11|pin@76||-10|10
35 Aschematic:wire|net@24|||900|pin@82||-11.5|-12.5|pin@81||-11.5|-14.5
36 ELSN[ZeroOrTwo]|LSN[TwoOrDone]|D5G2;X-9;|pin@13||B
37 ELSN[ZeroOrDone]|LSN[TwoOrOne]|D5G2;X-9.5;|pin@20||B
38 EMSN[ZeroOrTwo]|MSN[TwoOrDone]|D5G2;X8.5;|pin@17||B
39 EMSN[ZeroOrDone]|MSN[TwoOrOne]|D5G2;X9.5;|pin@19||B
40 EloadLO_1|disableLate|D5G2;|pin@83||I
41 Evdd_when_not_disabled|highWhenNotDisabled|D5G2;|pin@84||I
42 Eload||D5G2;X0.5;Y-3.5;|pin@78||I
43 EloadLO||D5G2;Y-3.5;|pin@80||I
44 Es[1:3]||D5G2;|pin@73||O
45 Eval_bar|valLO|D5G2;Y2;|pin@15||I
46 X