chips/omegaCounter/40nm/electric/purpleFive.delib/LEsettings.sch

   1 HpurpleFive|8.10k
   2
   3 # Cell LEsettings;2{sch}
   4 CLEsettings;2{sch}||schematic|1023920036000|1253147132016||ATTR_LESETTINGS(D6G1;HNPX-21;Y23;)I1|ATTR_alpha(D5G1;HNPX-18.5;Y25;)S0.7|ATTR_epsilon(D6G1;HNPX-21;Y28;)S0.01|ATTR_gate_cap(D6G1;HNPX-21;Y26;)S0.4|ATTR_keeper_ratio(D5G1;HNPX-17;Y24;)F0.1|ATTR_max_iter(D6G1;HNPX-21;Y27;)I40|ATTR_su(D6G1;HNPX-21;Y30;)S4.5|ATTR_wire_ratio(D6G1;HNPX-21;Y29;)S0.22|ATTR_x1inverter_length(D5G1;HNPX-18.75;Y17;)I4|ATTR_x1inverter_nwidth(D5G1;HNPX-18.75;Y18;)I12|ATTR_x1inverter_pwidth(D5G1;HNPX-18.75;Y19;)S24|ATTR_SPICE_template(D5G1;NTX-25;Y2;)S**LEsettings: None needed for LEsettings|prototype_center()I[12000,48000]
   5 ILEsettings;1{ic}|LEsettin@5||-1|0|||D5G4;|ATTR_LESETTINGS(D5G1;NPY-1.5;)I1|ATTR_alpha(D5G1;NPY0.5;)S0.7|ATTR_epsilon(D5G1;NPY3.5;)S0.01|ATTR_gate_cap(D5G1;NPY1.5;)S0.4|ATTR_keeper_ratio(D5G1;NPY-0.5;)F0.1|ATTR_max_iter(D5G1;NPY2.5;)I40|ATTR_su(D5G1;NPY5.5;)S4.5|ATTR_wire_ratio(D5G1;NPY4.5;)S0.22|ATTR_x1inverter_length(D5G1;NPY-3.5;)I4|ATTR_x1inverter_nwidth(D5G1;NPY-4.5;)I12|ATTR_x1inverter_pwidth(D5G1;NPY-5.5;)S24
   6 Ngeneric:Facet-Center|art@0||0|0||||AV
   7 Ngeneric:Invisible-Pin|pin@0||-9.5|12|||||ART_message(D6G1;)S[this is the diffusion effort of PMOS gates (Cdiffp/Cgate)]
   8 Ngeneric:Invisible-Pin|pin@1||-9.5|13|||||ART_message(D6G1;)S[this is the diffusion effort of NMOS gates (Cdiffn/Cgate)]
   9 Ngeneric:Invisible-Pin|pin@2||-9.5|14|||||ART_message(D6G1;)S[gate cap. is used to convert cap loads to gate loads (fF/lambda)]
  10 Ngeneric:Invisible-Pin|pin@3||-9.5|15|||||ART_message(D6G1;)S[this sets the maximum number of iterations]
  11 Ngeneric:Invisible-Pin|pin@4||-9.5|16|||||ART_message(D6G1;)S[epsilon is the convergence criterion]
  12 Ngeneric:Invisible-Pin|pin@5||-9.5|17|||||ART_message(D6G1;)S[wire ratio is the default wire ratio: Cwire/Cgate]
  13 Ngeneric:Invisible-Pin|pin@6||-9.5|18|||||ART_message(D6G1;)S[su is the global step-up (fan-out)]
  14 Ngeneric:Invisible-Pin|pin@7||-24|21|||||ART_message(D6G2;)S[This Facet is used to set Logical Effort Settings]
  15 Ngeneric:Invisible-Pin|pin@8||-9.5|11|||||ART_message(D6G1;)Sx1inverter_nwidth is the width of the nmos in an X=1 inverter
  16 Ngeneric:Invisible-Pin|pin@9||-9.5|10|||||ART_message(D6G1;)Sx1inverter_pwidth is the width of the pmos in an X=1 inverter
  17 Ngeneric:Invisible-Pin|pin@10||-9.5|9|||||ART_message(D6G1;)Sx1inverter_length is the length of the pmos and nmos in an X=1 inverter
  18 X