chips/omegaCounter/40nm/electric/purpleFive.delib/inv2iKnD.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell inv2iKnD;1{sch}
   8 Cinv2iKnD;1{sch}||schematic|1021415734000|1248729232899||ATTR_Delay(D5G1;HNPX-13.5;Y-8;)I100|ATTR_LEGATE(D5G1;HNPTX-13.5;Y-13;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-13.5;Y-9;)I-1|ATTR_X(D5G1;HNOJPX-13.5;Y-7;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-13.5;Y-11;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-12;)Sstrong1|ATTR_su(D5G1;HNPTX-13.5;Y-10;)I-1|prototype_center()I[0,0]
   9 IredFive:PMOS;1{ic}|PMOS@0||4.5|-5.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/10.
  10 Ngeneric:Facet-Center|art@0||0|0||||AV
  11 NOff-Page|conn@0||-10.5|-1|||Y|
  12 NOff-Page|conn@1||-10.5|1|||Y|
  13 NOff-Page|conn@2||15|0||||
  14 NOff-Page|conn@3||-4|6||||
  15 IredFive:inv2iCTLn;1{ic}|inv2iCTL@0||0|0|||D0G4;|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X
  16 Iinv2iKnD;1{ic}|inv2iKnD@0||28|12|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
  17 Ngeneric:Invisible-Pin|pin@0||1|9|||||ART_message(D5G2;)S["Set input in N, reset input is P"]
  18 Ngeneric:Invisible-Pin|pin@1||26.5|3|||||SIM_spice_card(D6G1;)S[.ic v(out) 'vhi']
  19 Ngeneric:Invisible-Pin|pin@2||0|15|||||ART_message(D5G2;)S[degradable two-input inverter with n-side keeper]
  20 Ngeneric:Invisible-Pin|pin@3||0|20|||||ART_message(D5G6;)S[inv2iKnD]
  21 Ngeneric:Invisible-Pin|pin@4||0|13|||||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
  22 Ngeneric:Invisible-Pin|pin@5||21.5|-14.5|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
  23 NWire_Pin|pin@6||4.5|0||||
  24 NWire_Pin|pin@7||-4.5|-5.5||||
  25 NWire_Pin|pin@8||-4.5|-1||||
  26 Ngeneric:Invisible-Pin|pin@9||27|-1|||||VERILOG_code(D6G1;)S[initial begin,     force out = 1;, #30000 release out;,end]
  27 NWire_Pin|pin@10||0|6||||
  28 NPower|pwr@0||4.5|-10.5||||
  29 Awire|net@0|||900|pin@6||4.5|0|PMOS@0|s|4.5|-3.5
  30 Awire|net@1|||1800|pin@7||-4.5|-5.5|PMOS@0|g|1.5|-5.5
  31 Awire|net@2|||900|PMOS@0|d|4.5|-7.5|pwr@0||4.5|-10.5
  32 Awire|net@3|||1800|conn@1|y|-8.5|1|inv2iCTL@0|inP|-2.5|1
  33 Awire|net@4|||2700|inv2iCTL@0|ctl|0|-2|pin@10||0|6
  34 Awire|net@5|||1800|inv2iCTL@0|out|2.5|0|pin@6||4.5|0
  35 Awire|net@6|||1800|pin@8||-4.5|-1|inv2iCTL@0|inN|-2.5|-1
  36 Awire|net@7|||1800|conn@0|y|-8.5|-1|pin@8||-4.5|-1
  37 Awire|net@8|||900|pin@8||-4.5|-1|pin@7||-4.5|-5.5
  38 Awire|net@9|||0|conn@2|a|13|0|pin@6||4.5|0
  39 Awire|net@10|||0|pin@10||0|6|conn@3|y|-2|6
  40 Ectl||D4G2;|conn@3|a|I|ATTR_le(D5G1;NY-2;)F0.67
  41 Ein[n]||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2;)F0.67
  42 Ein[p]||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-2;)F0.67
  43 Eout||D5G2;|conn@2|y|O|ATTR_le(D5G1;NY2;)D1.33
  44 X