chips/omegaCounter/40nm/electric/purpleFive.delib/invHT.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell invHT;2{sch}
   8 CinvHT;2{sch}||schematic|1021415734000|1159375620196||ATTR_Delay(D5G1;HNPX-12;Y-5;)I100|ATTR_LEGATE(D5G1;HNPTX-12;Y-10;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-6;)I-1|ATTR_X(D5G1;HNOJPX-12;Y-4;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-12;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-9;)Sstrong1|ATTR_su(D5G1;HNPTX-12;Y-7;)I-1|ATTR_verilog_template(D5G1;NTX6.5;Y-13;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||-10|0||||
  11 NOff-Page|conn@1||9.5|0||||
  12 IredFive:invHT;1{ic}|invHT@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
  13 IinvHT;1{ic}|invHT@1||15|10|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
  14 Ngeneric:Invisible-Pin|pin@0||-2.5|13.5|||||ART_message(D5G2;)S[P to N width ratio is 4 to 1]
  15 Ngeneric:Invisible-Pin|pin@1||13.5|-10|||||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
  16 Ngeneric:Invisible-Pin|pin@2||-2|15.5|||||ART_message(D5G2;)S[HI-threshold inverter]
  17 Ngeneric:Invisible-Pin|pin@3||-1|20.5|||||ART_message(D5G6;)S[invHT]
  18 Awire|net@0|||0|invHT@0|in|-2.5|0|conn@0|y|-8|0
  19 Awire|net@1|||1800|invHT@0|out|2.5|0|conn@1|a|7.5|0
  20 Ein||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY-1.5;)F1.67
  21 Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;NY1.5;)F1.67
  22 X