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[fleet.git] / chips / omegaCounter / 40nm / electric / purpleFive.delib / nand2LT_sy.sch
1 HpurpleFive|8.10k
2
3 # External Libraries:
4
5 LredFive|redFive
6
7 # Cell nand2LT_sy;1{sch}
8 Cnand2LT_sy;1{sch}||schematic|1021415734000|1159375698504||ATTR_Delay(D5G1;HNPX-17;Y-10.5;)I100|ATTR_LEGATE(D5G1;HNPTX-17;Y-13.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-17;Y-8.5;)I-1|ATTR_X(D5G1;HNOJPX-17;Y-7.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-17;Y-11.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-17;Y-12.5;)Sstrong1|ATTR_su(D5G1;HNPTX-17;Y-9.5;)I-1|prototype_center()I[0,0]
9 Ngeneric:Facet-Center|art@0||0|0||||AV
10 NOff-Page|conn@0||-17.25|2.5||||
11 NOff-Page|conn@1||16.5|0|||Y|
12 NOff-Page|conn@2||-17.5|-2.5|||Y|
13 IredFive:nand2LT_sy;1{ic}|nand2LT_@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2.5;Y-3;)S@Delay|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)S@X|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
14 Inand2LT_sy;1{ic}|nand2LT_@1||33.25|20.75|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-2.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.5;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
15 NWire_Pin|pin@12||-7.5|1||||
16 NWire_Pin|pin@13||-7.5|2.5||||
17 NWire_Pin|pin@14||-7.5|-1||||
18 NWire_Pin|pin@15||-7.5|-2.5||||
19 Ngeneric:Invisible-Pin|pin@26||-2|16|||||ART_message(D5G2;)S[Sized assuming inputs go low together]
20 Ngeneric:Invisible-Pin|pin@27||15|-14.5|||||ART_message(D5G2;)S[X is drive strength,The pull-down is twice as strong as,one pull-up; or both pull-ups together,are as strong as the pull-down]
21 Ngeneric:Invisible-Pin|pin@28||-2|18|||||ART_message(D5G2;)S[P to N width ratio is 1 to 2]
22 Ngeneric:Invisible-Pin|pin@29||-2|20|||||ART_message(D5G2;)S[symetric LO-threshold NAND]
23 Ngeneric:Invisible-Pin|pin@30||-2|25|||||ART_message(D5G6;)S[nand2LT_sy]
24 Awire|net@0|||0|nand2LT_@0|ina|-2.5|-1|pin@14||-7.5|-1
25 Awire|net@2|||0|nand2LT_@0|inb|-2.5|1|pin@12||-7.5|1
26 Awire|net@27|||2700|pin@12||-7.5|1|pin@13||-7.5|2.5
27 Awire|net@28|||900|pin@14||-7.5|-1|pin@15||-7.5|-2.5
28 Awire|net@38|||0|conn@1|a|14.5|0|nand2LT_@0|out|2.5|0
29 Awire|net@43|||0|pin@13||-7.5|2.5|conn@0|y|-15.25|2.5
30 Awire|net@44|||1800|conn@2|y|-15.5|-2.5|pin@15||-7.5|-2.5
31 Eina||D5G2;|conn@2|a|I|ATTR_le(D5G1;NY2;)I1
32 Einb||D5G2;|conn@0|a|I|ATTR_le(D5G1;NY2;)I1
33 Eout||D5G2;|conn@1|y|O|ATTR_le(D5G1;NY-2;)F1.33
34 X