chips/omegaCounter/40nm/electric/purpleFive.delib/triInv.sch

   1 HpurpleFive|8.10k
   2
   3 # External Libraries:
   4
   5 LredFive|redFive
   6
   7 # Cell triInv;1{sch}
   8 CtriInv;1{sch}||schematic|1021415734000|1159376021331||ATTR_Delay(D5G1;HNPX-12;Y-5.5;)I100|ATTR_LEGATE(D5G1;HNPTX-12;Y-10.5;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-6.5;)I-1|ATTR_X(D5G1;HNOJPX-12.5;Y-4.5;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-12;Y-7.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-8.5;)Sstrong1|ATTR_su(D5G1;HNPTX-12;Y-9.5;)I-1|prototype_center()I[0,0]
   9 Ngeneric:Facet-Center|art@0||0|0||||AV
  10 NOff-Page|conn@0||0.5|8|||RRR|
  11 NOff-Page|conn@1||0.5|-7|||R|
  12 NOff-Page|conn@2||-14|0||||
  13 NOff-Page|conn@3||11|0||||
  14 Ngeneric:Invisible-Pin|pin@0||-1.5|24|||||ART_message(D5G6;)S[invTri]
  15 Ngeneric:Invisible-Pin|pin@1||-2|18.5|||||ART_message(D5G2;)S[one-parameter tri-state inverter]
  16 Ngeneric:Invisible-Pin|pin@2||19|-14|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
  17 Ngeneric:Invisible-Pin|pin@3||-2|15.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
  18 IredFive:triInv;1{ic}|triInv@0||0.5|0|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-1.5;)S@Delay|ATTR_X(D5G1.5;NOJPX2.5;Y2;)S@X
  19 ItriInv;1{ic}|triInv@1||28.5|17|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-1.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)S""
  20 Awire|net@0|||2700|triInv@0|enB|0.5|2|conn@0|y|0.5|6
  21 Awire|net@1|||900|triInv@0|en|0.5|-2|conn@1|y|0.5|-5
  22 Awire|net@2|||1800|conn@2|y|-12|0|triInv@0|in|-2|0
  23 Awire|net@3|||1800|triInv@0|out|3|0|conn@3|a|9|0
  24 Een||D5G2;|conn@1|a|I|ATTR_le(D5G1;NX-1;)F0.6667
  25 EenB||D5G2;|conn@0|a|I|ATTR_le(D5G1;NX-2;Y2;)F1.333
  26 Ein||D5G2;|conn@2|a|I|ATTR_le(D5G1;NY-2;)I2
  27 Eout||D5G2;|conn@3|y|O|ATTR_le(D5G1;NY2;)I2
  28 X